Shift Register Circuit With Boosting Unit For High Clock Frequency Drive
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Solution Overview
Problem
Conventional gate line driving circuits face challenges in maintaining high drive capability of transistors when the frequency of the clock signal increases, leading to decreased performance and difficulty in achieving high resolution in display apparatuses.
Innovation Solution
The proposed shift register circuit includes a pull-up driving circuit and a pull-down driving circuit, with a boosting unit that enhances the voltage of a third node connected to the control electrode of a third transistor, allowing the first node to be pre-charged to a higher level even at higher clock frequencies, preventing a decrease in drive capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the clock signal is increased to improve the operation speed of the gate line driving circuit, then the productivity is improved, but the drive capability of the first transistor decreases due to insufficient pre-charge time of the first node
Solution Approach 1:
The invention applies preliminary action by pre-charging the third node (gate of third transistor) before the first node charging operation. The third transistor is turned on in advance through the boosting unit that raises the third node voltage to a level higher than the power supply voltage, preparing the charging path before it is needed, thus ensuring fast charging even at high clock frequencies
Solution Approach 2:
The invention changes the voltage parameter of the third node from the normal power supply voltage level to a boosted level higher than the power supply voltage. This parameter change enables the third transistor to have enhanced drive capability during the pre-charge phase, allowing the first node to be charged to the required voltage level within the shortened time window at high clock frequencies
2Productivity
If the pulse width of the input signal is reduced to accommodate higher clock frequencies, then the productivity is improved, but the first node cannot attain the maximum pre-charge level due to the narrow charging window
Solution Approach 1:
The invention applies preliminary anti-action by counteracting the effect of narrow pulse width through the boosting unit. Instead of waiting for the limited pulse duration to charge the first node, the third transistor is activated in advance with boosted voltage to create a strong charging current path that compensates for the reduced charging time, ensuring the first node reaches the maximum pre-charge level even with narrow input signal pulses
3Device complexity
If the third transistor operates in source-follower mode during pre-charge, then the device complexity is reduced, but the drive capability decreases as the first node voltage increases
Solution Approach 1:
The invention changes the gate voltage parameter of the third transistor from the input signal level to a boosted level higher than the power supply voltage. This parameter change transitions the third transistor's operation from source-follower mode (where drain current decreases as source voltage increases) to a mode where it can maintain high drive capability throughout the charging process, as the enhanced gate-to-source voltage difference compensates for the increasing source voltage
Data Source
AI summary
A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.