Semiconductor Memory Address Counting for Parasitic Capacitance
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Solution Overview
Problem
Highly integrated semiconductor memory apparatuses face misoperation due to parasitic capacitance between signal and power lines, which prevents the internal voltage from being effectively transferred to the internal circuit, leading to unstable operation.
Innovation Solution
A semiconductor memory apparatus is designed with a counting control circuit and an address counting circuit that generate specific start signals and control signals to manage count addresses, ensuring only specified addresses are counted during activation, thereby stabilizing the internal voltage and preventing misoperation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor memory apparatus is highly integrated to increase capacity, then the storage capacity is improved, but the parasitic capacitance between power lines increases causing misoperation
Solution Approach 1:
The patent segments the auto-refresh operation into two distinct phases: a first phase that counts all bit line addresses, and a second phase that counts only specified bit line addresses. This segmentation allows the system to handle the parasitic capacitance issue by controlling which addresses are activated in different time periods, preventing misoperation while maintaining high integration capacity.
2Reliability
If all bit line addresses are counted during auto-refresh, then the refresh coverage is improved, but misoperation occurs due to parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by first counting all bit line addresses in the first auto-refresh phase before proceeding to count only specified addresses in the second phase. This preliminary counting ensures that all memory blocks are initially refreshed, establishing a safe state before the restricted counting phase begins, thereby preventing misoperation while maintaining comprehensive refresh coverage.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the counting behavior of the address counting circuit based on the phase of the auto-refresh operation. During the first phase, the circuit counts all bit line addresses; during the second phase, it counts only specified addresses. This dynamic adaptation allows the system to optimize refresh coverage while avoiding parasitic capacitance-induced misoperation in different operational contexts.
3Speed
If the internal voltage is generated quickly to the target level, then the activation speed is improved, but the voltage cannot be effectively transferred to internal circuits due to parasitic capacitance
Solution Approach 1:
The patent employs periodic action by dividing the auto-refresh operation into distinct periodic phases: a first phase for counting all bit line addresses and a second phase for counting only specified addresses. This periodic structure allows the internal voltage to be generated and transferred in controlled intervals, ensuring that voltage transfer effectiveness is maintained while preserving fast activation speed through efficient address counting sequences.
Data Source
AI summary
A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal.