PSRAM Burst Read Write Controller Using Multiple Page Addresses
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Solution Overview
Problem
Existing low pin count memories, such as HyperRAM, do not support high-speed access throughput, and conventional pseudo static random access memory (PSRAM) cannot update read and write addresses without entering a standby mode, leading to low data transmission efficiency and access throughput due to the DQ bus being occupied by data signals during operations.
Innovation Solution
A memory apparatus and burst read/write method that provide multiple page starting addresses during burst operations, allowing the pseudo static random access memory to perform operations without entering a standby mode, thereby improving data occupancy and access efficiency on the DQ bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the pseudo static random access memory enters a standby mode to update addresses and commands, then the DQ bus can be freed for other operations, but the data transmission efficiency and access throughput are reduced due to the operation pause
Solution Approach 1:
The patent segments the address and command input process from the data transfer process by utilizing separate input latches (first input latch and second input latch) that can independently receive and hold address/command signals and data signals respectively. This segmentation allows the DQ bus to be divided into different functional phases without requiring a complete standby mode, thereby maintaining data transmission efficiency while enabling address updates.
Solution Approach 2:
The patent implements preliminary action by pre-loading addresses and commands into input latches during idle periods or before data transfer operations. The first input latch receives and holds address/command signals in advance, and the second input latch prepares data signals beforehand. This preliminary preparation eliminates the need to pause operations for address updates, thus preventing productivity loss while ensuring DQ bus availability when needed.
2Reliability
If the DQ bus is occupied by data signals during read or write operations, then data transmission is ensured, but the read address and write address cannot be updated without entering standby mode
Solution Approach 1:
The patent introduces intermediary elements (first input latch and second input latch) that mediate between the DQ bus and the pseudo static random access memory. These latches act as buffer intermediaries that can temporarily hold address/command signals and data signals separately. This intermediary mechanism allows address updates to occur through the latch structure without directly occupying the DQ bus during critical data transfer operations, thereby maintaining both data transmission reliability and address update adaptability.
Solution Approach 2:
The patent adds a temporal dimension to the address update process by using sequential latch operations. Instead of attempting to update addresses simultaneously with data transfer (which would cause bus conflicts), the system uses the time dimension to sequence operations: addresses are latched in advance or during permissible windows, then data transfer proceeds on the DQ bus without interruption. This dimensional separation resolves the conflict between data transmission reliability and address update versatility.
3Productivity
If multiple page starting addresses are provided during burst operations, then burst access efficiency is improved, but the controller and memory interface complexity increases
Solution Approach 1:
The patent merges multiple address input operations into a single unified latch structure that can accept multiple page starting addresses simultaneously or in rapid succession. The first input latch is designed to receive and hold multiple address signals, consolidating what would otherwise require separate handling circuits. This merging approach enables burst access to multiple pages without proportionally increasing controller complexity, as the latch structure handles multiple addresses through a single integrated mechanism.
Data Source
AI summary
A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, and the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to a sequence of receiving the page starting addresses.