Address Control Circuit Skew Reduction in Semiconductor Memory
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Solution Overview
Problem
In semiconductor memory devices, particularly in mobile applications, there is a skew in transmission times between column address paths and data paths during write operations due to differences in path lengths, leading to inefficiencies in data transfer.
Innovation Solution
The implementation of a write column address control circuit that generates a write column address during a specific burst period, synchronized with the data transfer, to align the write operation with the data path, reducing the skew between address and data transmission times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the column address control circuit is placed at the opposite edge region from the data input/output circuit, then the device layout is optimized for mobile applications, but a skew is generated between transmission times of column address and data during write operations
Solution Approach 1:
The patent segments the address control functionality into two separate circuits: a read column address control circuit and a write column address control circuit. This segmentation allows each circuit to be optimized for its specific operation mode, with the write column address control circuit positioned to minimize skew with the data input/output circuit while the read column address control circuit maintains the edge-region layout for mobile applications.
Solution Approach 2:
The patent introduces a write column address control circuit as an intermediary component between the column address control circuit and the memory cell array. This intermediary circuit generates the write column address during a specific burst period and transmits it through a write column address path that is optimized to match the data path length, thereby eliminating the transmission skew.
2Device complexity
If the column address path and data path have different lengths, then the circuit design is simplified, but transmission skew occurs between column address and data during write operations
Solution Approach 1:
The patent implements dynamic path selection by creating separate column address paths for read and write operations. The write column address path is dynamically configured to have the same length as the data path, while the read column address path maintains its original length. This dynamic adaptation eliminates skew in write operations without complicating the overall circuit design.
Solution Approach 2:
The patent changes the parameter of path length by creating a write column address path with a specific length that matches the data path length. This parameter adjustment is achieved by routing the write column address through optimized pathways that compensate for any length differences, thereby eliminating transmission skew while maintaining circuit simplicity.
Data Source
AI summary
An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode.