Digital Storage TRIZ Cases

Shared RSLF sources boost discharge capacity, reducing memory access time despite increased device complexity from coupled circuits.

A stacked magnetic tunnel junction unit uses a shared pinning layer to reduce stack height while enabling multi-bit storage through distinct switching thresholds.

A latching sense amplifier uses inverted pull-up circuits to reduce power consumption.

A memory circuit read method applies a high-amplitude pulse to activate the selector followed by a lower voltage to maintain the state.

Double-sided bipolar decoders drive access lines from both ends, reducing current and voltage spikes near drivers while improving delivery to distant cells.

A data writing apparatus transmits aligned even and odd data through distributed transmission units at mutually different timings.

A semiconductor device uses complementary bit lines and dummy cells to balance capacitances during read operations.

A dual read word line design segments bit cell access to conserve power during memory operations.

Conformal and non-conformal spacer layers with overhang structures protect memory units, reducing damage risk and improving manufacturing yield.

A semiconductor memory bank uses temperature sensors to generate voltage signals that adjust command timing parameters.

Through electrodes and an interface chip maintain constant bank numbers across layers, resolving refresh control complexity in stacked DRAM.

Vertical thin film transistors stack memory cells above a substrate, increasing density without expanding the footprint.

A nonvolatile static random access memory cell uses resistive switching devices coupled to bit lines for data storage.

A single reference cell design generates a precise reference current for MRAM read circuits using MOSFETs and a sense amplifier.

Inverting MTJ pinned and free layer order suppresses source voltage increase, maintaining current driving capability despite processing alignment constraints.

Spin orbit torques alternate pinned domain walls in converging buses to eliminate external magnetic fields and reduce energy requirements.

Hardware logic reads an initialization register to selectively initialize SRAM partitions, preventing data loss during warm reboots while reducing area costs.

Input-output circuit performs multiple-input shift register function using shared timing conditions.

Segmented control signals enable selective data masking on local lines, preventing transmission errors while managing circuit complexity.

A memory device manages master word line voltage pulses to reduce power consumption during access operations.

A voltage generating circuit determines read voltage codes based on memory cell switching states to adapt read voltages.

Hybrid material storage cells switch fluorescent states under external force, resolving mechanical damage and low density limits of conventional binary systems.

A multi-level dynamic memory device uses MOS-type correction capacitors connected in parallel to coupling capacitors, with capacitance adjusted by a control voltage signal.

Capacitor-driven write driver compensates for floating bitline leakage currents, ensuring negative voltage stability during extended write operations.

A semiconductor memory cell uses a double gate structure with parallel MOSFETs to deliver sufficient current drivability.

A memory device uses a clock activation circuit to generate an enable signal based on commands, activating a second clock only during data operations.

Segmenting the RRAM chip into regions with high voltage and high dielectric constant layers resolves the trade-off between storage time and computing speed.

Clamping control signal generating circuit adjusts clamping current for phase change memory read operations.

Synchronizing external and internal refresh signals reduces latency when exiting self-refresh mode, improving system performance.

Dual-pipe memory circuitry captures address pairs to reduce bank conflicts and improve operational efficiency.

Interlinking MOSFET gates between bit lines blocks sub-threshold leak currents while shrinking cell footprint by 40 percent for high-density cache applications.

Unified mat selection circuits minimize chip area and power consumption by standardizing circuit structures across edge and non-edge mats.

A sum address compare function generates partial lookup values within memory cells to accelerate virtual to physical address translations.

A memory controller sends command and address packets with error detection data to a semiconductor memory device.

Write column address control circuit aligns transmission times to eliminate skew between column address and data paths during write operations.

Time delay selectors isolate target signals from sneak currents in crossbar arrays, reducing power consumption and improving read accuracy.

Current integrator circuits isolate switching charge from dielectric interference, eliminating parasitic capacitance effects on bit-lines.

A cross-connect switch dynamically allocates shared sense amplifiers and row buffers across multiple memory banks to enable coincident access.

Segmented droop and negative bit line units resolve SRAM write failures from threshold variations without increasing layout area or power consumption.

Word line assist circuit uses voltage differentials to transition SRAM word lines, reducing propagation delay without adding re-buffers.

Shared access control circuits route boost signals through capacitors to raise word line voltage, reducing write failures at low supply levels.

Transition protection unit stabilizes data strobe signal transitions using a control signal and decoupling capacitor.

Segmented PMOS and NMOS circuits compensate threshold voltage differences, improving sensing margin in DRAM devices.

Segmenting single port memory into independent banks with dual wordlines resolves compiler accuracy errors while enabling simultaneous bank access.

Local word line gating units disable defective memory cells in crossbar arrays to prevent current aggregation.

A sense amplifier circuit disconnects bit lines from the sensing node using feedback control.

Segmenting banks into sub-banks for normal data and metadata minimizes row hammer effects while reducing area overhead.

Slower clock signal determines fly-by delays in sequential memory topology, resolving measurement precision trade-offs.

Extension logic in a DRAM data driver selectively delays signals to synchronize timing, reducing reliance on expensive DLL circuits.