Shared Access Control Circuit Voltage Boosting for SRAM Write Reliability
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Solution Overview
Problem
Designing robust SRAM semiconductor memories that can successfully write and read data across all operational voltage ranges is challenging due to increasing variations in device properties, making it difficult to reduce voltage levels without incurring significant area overhead and efficiency losses.
Innovation Solution
A semiconductor memory device with routing circuitry that generates and routes a boost signal to selected access control lines using a delay circuit, providing a voltage boost to access control lines, thereby increasing the chances of successful data writing and reading, while minimizing area overhead and avoiding timing/power waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a boost transistor is added per word line to generate boosted voltage, then write capability at low voltage is improved, but area overhead increases significantly
Solution Approach 1:
The patent merges the boost functionality into a shared access control circuit that serves multiple word lines. Instead of having dedicated boost transistors on each word line, a single access control circuit with a capacitor provides boosted voltage to multiple selected word lines through shared routing, significantly reducing area overhead while maintaining write capability.
Solution Approach 2:
The access control circuit is designed to perform multiple functions: normal word line activation, boosted voltage generation for writes, and selective routing to different word lines. This multi-functional design eliminates the need for separate boost circuits while maintaining robust write capability across all word lines.
2Device complexity
If the PMOS pass gate signal is shorted to the back of the capacitive coupling transistor, then circuit complexity is reduced, but turn-off delay increases causing charge leakage
Solution Approach 1:
The patent segments the control signals for the PMOS pass gate and the capacitive coupling transistor, allowing independent control of each. The access control circuit generates separate control signals that enable precise timing control, ensuring the PMOS turns off completely before the capacitor couples charge to the word line, thereby eliminating charge leakage while maintaining reasonable circuit complexity.
3Use of energy by moving object
If voltage levels are reduced to lower power consumption, then power efficiency is improved, but write reliability deteriorates due to insufficient voltage to switch feedback loop state
Solution Approach 1:
The patent employs periodic pulsing of the word line voltage through the access control circuit. A capacitor is charged during a precharge phase and then discharged in a controlled pulse to provide the necessary voltage boost to the selected word line. This periodic action allows the system to operate at low average power while providing high-voltage pulses when write operations are needed, thus maintaining write reliability without increasing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the probability of successful data writing and reading, particularly at low voltage levels, by providing a controlled voltage boost to access control lines, reducing write failures, and maintaining memory efficiency with centralized control of the boost signal delay.
Implementation Method 1
to couple said boost signal to said access control line through said capacitor of said access control circuit
Data Source
AI summary
A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access control line and to couple the boost signal to the access control line through the capacitor of the access control circuit to provide a boost to a voltage level on the access control line.