Section Selection Circuits for Memory Mat Area Reduction
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Solution Overview
Problem
The inconsistency in the number of word lines and alignment of bit lines and memory cells between non-edge mats and edge mats in semiconductor memory devices leads to increased chip area and power consumption due to the need for different circuit structures in mat selection circuits.
Innovation Solution
By dividing each edge mat and non-edge mat into sections with the same size, and using section selection circuits with similar circuit structures, the number of wirings is reduced, thereby minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different circuit structures are used for mat selection circuits in non-edge mats and edge mats, then memory access functionality is achieved, but chip area increases
Solution Approach 1:
The patent applies universality by designing a unified mat selection circuit structure that can handle both non-edge mats and edge mats through a single standardized configuration. The section selection circuits use the same circuit topology for all mats, with the address decoder generating appropriate selection signals for different mat types, thereby reducing chip area while maintaining full memory access functionality.
Solution Approach 2:
The patent segments the memory array into multiple sections within each mat, allowing the use of standardized section selection circuits that can be replicated across all mats. This segmentation enables the address decoder to selectively activate specific sections based on the target mat type, achieving versatile access control with a uniform circuit structure.
2Adaptability or versatility
If different circuit structures are used for mat selection circuits in non-edge mats and edge mats, then memory access functionality is achieved, but power consumption increases
Solution Approach 1:
The unified mat selection circuit structure reduces power consumption by eliminating the need for multiple different circuit implementations. The standardized section selection circuits consume consistent power regardless of whether they are accessing non-edge or edge mats, and the address decoder efficiently generates selection signals without requiring additional power-intensive customization logic.
3Length of stationary object
If folded bit line structure is used in edge mats, then bit line length is equalized, but mat selection circuit complexity increases
Solution Approach 1:
The patent resolves the complexity issue by designing a universal mat selection circuit that handles both folded and non-folded bit line configurations through the same circuit topology. The address decoder automatically generates the appropriate selection signals based on the target mat type, eliminating the need for different circuit structures despite the physical differences in bit line arrangements.
Data Source
AI summary
Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.