Double-Sided Asymmetric Decoders for Memory Access Line Uniformity

The patent divides the decoder functionality into two separate decoders positioned at opposite ends of the access lines. This segmentation allows each decoder to serve a specific region, reducing the maximum distance any memory cell must be driven and balancing the parasitic load distribution. The first decoder couples to a first end of access lines while the second decoder couples to a second end, creating two independent driving sources that work in concert to achieve uniform signal delivery across the entire memory array.

The patent transitions from a one-sided decoder architecture to a two-sided architecture, effectively adding a spatial dimension to the signal distribution. By placing decoders at both ends of the access lines, the maximum distance any memory cell must be driven is halved, and the resistance path is distributed across two parallel paths instead of one long path. This dimensional change enables larger memory arrays to be built without sacrificing current delivery amplitude to distant cells.

The patent segments the memory array into two regions, each served by a dedicated decoder positioned at opposite ends. This segmentation ensures that no memory cell is too close to a single decoder, which would cause excessive current draw and voltage spikes. Instead, each cell receives balanced drive strength from its nearest decoder without the harmful effects of being overly close to a high-current source.