STT-MRAM Cell Area Reduction via Blocking MOSFETs
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Solution Overview
Problem
STT-MRAM memory cells require further miniaturization to achieve high-speed and large-capacity performance, while also addressing issues of area occupation and access time, particularly due to sub-threshold current leaks in matrix configurations.
Innovation Solution
A semiconductor memory device configuration featuring a pair of MTJs connected in series with multiple MOSFETs, where the gate connections of certain MOSFETs are interlinked to optimize current flow and reduce area usage, incorporating a shared sense circuit among memory cells to minimize overall size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a matrix shape to increase capacity, then storage density is improved, but sub-threshold current leaks from MOSFETs to MTJs multiply and generate excessive leak current
Solution Approach 1:
The patent extracts the harmful sub-threshold leak current path by introducing a dedicated blocking MOSFET between the MOSFET and MTJ. This blocking MOSFET is specifically designed to prevent leak current while allowing legitimate signal current to pass during active operations, thereby extracting the harmful element from the system without compromising functionality.
Solution Approach 2:
The blocking MOSFET acts as an intermediary element inserted between the MOSFET and MTJ. It mediates the current flow by blocking sub-threshold leak current while permitting normal operation current to pass through when properly activated, thus resolving the contradiction between maintaining low leak current and ensuring proper signal transmission.
2Loss of energy
If conventional power gating methods are used to reduce leak current, then power consumption is improved, but wake up time increases and operating current increases
Solution Approach 1:
Instead of applying power gating globally to entire rows or columns, the patent applies local quality control by placing individual blocking MOSFETs at specific cell locations where leak current is most problematic. This localized approach allows selective blocking of leak current paths without affecting the entire array, enabling faster wake-up times and lower operating current compared to coarse power gating methods.
3Measurement precision
If differential pair configuration with two MTJs is used to improve output signal strength, then sensing capability is improved, but area occupied by memory cell increases
Solution Approach 1:
The patent merges the differential pair configuration with the blocking MOSFET structure, combining multiple functions into a unified cell design. The two MTJs are arranged in a differential pair for improved sensing, while blocking MOSFETs are integrated into the same structure to prevent leak current, achieving both high signal strength and low area occupation through functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the area occupied by memory cells by approximately 40% compared to conventional designs, enhances access speed, and maintains low power consumption, making it suitable for high-density applications like cache memory.
Implementation Method 1
Spin transfer torque-magnetoresistive random access memory (STT-MRAM) is attracting attention as memory that uses a magnetic tunneling junction (MTJ) device, which is a memory device in which resistance can change.
Implementation Method 2
a magnetic tunneling junction (MTJ) device, which is a memory device in which resistance can change
Data Source
AI summary
A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a).