NVSRAM Cell Resistive Switching Without Control Lines
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Solution Overview
Problem
Conventional non-volatile static random access memory (NVSRAM) cells face issues with high power consumption due to current leakage, especially as memory capacity increases, and require external control lines that occupy layout area and prolong boot times.
Innovation Solution
A NVSRAM cell design utilizing bipolar resistive-switching devices without an external control line, where resistive-switching devices are connected directly to bit lines through switch devices, allowing for reduced power consumption and layout area, and enabling faster operation by eliminating the need for external control lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NVSRAM uses external control lines to manage resistive-switching devices, then the devices can be properly controlled for data storage, but the layout area increases and boot time is prolonged
Solution Approach 1:
The patent extracts and eliminates the external control line from the NVSRAM structure. The resistive-switching device is directly integrated with the SRAM cell without requiring separate control lines, thereby reducing layout area while maintaining data storage functionality through the inherent switching behavior of the resistive device when bit line voltages are applied
Solution Approach 2:
The bit line and complementary bit line serve dual functions: they act as data access lines for SRAM operations and simultaneously serve as control lines for switching the resistive-switching device between high and low resistance states. This eliminates the need for separate control lines during write and recall operations
2Reliability
If conventional NVSRAM uses external control lines, then resistive-switching devices can be controlled for data storage, but power consumption increases
Solution Approach 1:
The patent removes the external control line structure that consumed additional power during switching operations. The resistive-switching device is now controlled solely by the bit line voltage transitions during normal SRAM read/write operations, eliminating the need for separate control signal generation and distribution that would consume power
Solution Approach 2:
The bit lines perform multiple functions including data writing, reading, and controlling the resistive-switching device state transitions. By consolidating these functions into existing signal paths rather than adding separate control lines, the patent reduces overall power consumption while maintaining full functionality
3Speed
If SRAM is used for high-speed operation, then accessing speed is high, but power consumption increases due to current leakage in standby mode
Solution Approach 1:
Before the SRAM enters standby mode, the data is written in advance to the resistive-switching device which maintains data through its resistance state (high or low resistance) without requiring power. When power is restored, the data is automatically recalled from the resistive device to the SRAM cell, eliminating the need for continuous power during standby while maintaining high-speed access capability
Solution Approach 2:
The patent changes the storage state parameter from voltage-dependent (SRAM) to resistance-dependent (resistive-switching device). The resistive device maintains data through its physical resistance state which is non-volatile, allowing the SRAM to be powered down during standby while preserving data, thus reducing power consumption without sacrificing access speed when powered
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption, minimizes current leakage, and decreases the load on bit lines, enhancing read times and overall performance while maintaining high-speed operations similar to SRAM.
Implementation Method 1
the resistive-switching device has a resistance state, i.e., a high resistance state or a low resistance state
Implementation Method 2
Gates of the switch device are coupled to a switch line for receiving a switching signal to control conduction of the resistive-switching device to the bit line
Data Source
AI summary
A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.