Semiconductor Memory Cell Double Gate Structure for Write Current
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Solution Overview
Problem
The spin momentum transfer writing system for magnetic random access memory faces challenges in achieving sufficient current density for magnetization reversal, leading to increased write current requirements due to miniaturization, and the 2Tr-1MTJ configuration increases cell size for high integration, making it difficult to achieve practical application with high reliability and low power consumption.
Innovation Solution
A semiconductor memory cell array with a double gate structure, where memory cells are arranged in a hound's tooth layout with two MOSFETs and one resistance change element, reducing cell size by half and utilizing Gray code address mapping to simplify the row decoder and reduce chip size, allowing for efficient current drivability and high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the spin momentum transfer writing system is used with miniaturized memory cells, then the current density for magnetization reversal decreases, but the write current becomes excessively large
Solution Approach 1:
The patent combines two MOSFETs in parallel to form a single memory cell, creating a 2Tr-1MTJ configuration. This merging of transistor resources allows the cell to deliver sufficient write current density even as individual cell dimensions are reduced, resolving the contradiction between miniaturization and maintaining adequate current for magnetization reversal
Solution Approach 2:
The patent transitions from a 1Tr-1MTJ configuration to a 2Tr-1MTJ configuration, adding an additional transistor dimension to the memory cell structure. This dimensional change in the circuit architecture enables improved current drivability without increasing the physical footprint proportionally, as transistors can be arranged in parallel within the same cell area
2Power
If the 2Tr-1MTJ configuration is used to increase current drivability, then the write current becomes sufficient, but the cell size increases
Solution Approach 1:
The patent merges two MOSFETs into a single functional memory cell unit, where the transistors share common bit lines and control structures. This consolidation allows the cell to achieve doubled current drivability while minimizing the area increase through efficient spatial arrangement and resource sharing
Solution Approach 2:
The patent designs the 2Tr-1MTJ cell with multi-functional transistors that serve both as access devices and as current amplification elements. The shared bit lines and control logic provide universal functionality across the memory array, reducing redundant structures and optimizing cell density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate structure achieves a memory cell size comparable to DRAMs, enabling cost-effective high-capacity nonvolatile memory with improved current drivability and reduced power consumption, making it suitable for practical application.
Implementation Method 1
The magnetic random access memory enables the storage of binary data by utilization of the magnetoresistive effect
Implementation Method 2
As for the magnetoresistive effect, it is general to utilize a tunneling magnetoresistive (TMR) effect
Implementation Method 3
a spin momentum transfer writing system utilizing a spin torque due to a flowing of spin-polarized electrons through the MTJ element
Data Source
AI summary
The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.