Offset Compensated Sense Amplifier for DRAM
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face accuracy and performance degradation due to offset noise in sense amplifiers, caused by variations in inter-device characteristics such as threshold voltages.
Innovation Solution
An offset compensated sense amplifier is designed with a first sense amplifier circuit including PMOS transistors and a second sense amplifier circuit including NMOS transistors, along with isolation and equalization circuits. The sense amplifier performs offset compensation operations based on threshold voltage differences between transistors to reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sense amplifier circuits are used, then device complexity is reduced, but offset noise increases due to threshold voltage variations
Solution Approach 1:
The sense amplifier is divided into two separate circuits: a first sense amplifier circuit for NMOS transistors and a second sense amplifier circuit for PMOS transistors. Each circuit independently compensates for threshold voltage offsets of its respective transistor type, allowing complex offset compensation functionality to be segmented into manageable parts that reduce overall circuit complexity while maintaining high sensing accuracy.
Solution Approach 2:
An isolation circuit is introduced as an intermediary between the first and second sense amplifier circuits. This isolation circuit prevents interference between the NMOS and PMOS compensation operations, enabling each circuit to function independently without mutual interference, thus maintaining circuit simplicity while achieving reliable offset compensation.
2Measurement precision
If offset compensation operations are performed, then sensing margin increases, but operation time increases
Solution Approach 1:
The offset compensation operation is implemented as a periodic preliminary action that is performed once before the main sensing operation. By completing the threshold voltage offset compensation in advance through the first and second sense amplifier circuits, the actual sensing operation can proceed quickly without repeated compensation cycles, thus increasing sensing margin while minimizing time loss.
Solution Approach 2:
The offset compensation is performed as a preliminary action before the actual data sensing operation. The first sense amplifier circuit compensates for NMOS threshold voltage offsets and the second circuit compensates for PMOS threshold voltage offsets in advance, establishing optimal operating conditions before the critical sensing measurement begins, thereby improving sensing margin without significantly increasing total operation time.
3Manufacturing precision
If separate sense amplifier circuits for NMOS and PMOS are used, then offset compensation accuracy improves, but device complexity increases
Solution Approach 1:
The sense amplifier system is segmented into specialized circuits: the first sense amplifier circuit handles NMOS threshold voltage offset compensation while the second sense amplifier circuit handles PMOS threshold voltage offset compensation. This segmentation allows each circuit to be optimized for its specific transistor type, improving offset compensation accuracy while keeping individual circuit blocks relatively simple and manageable.
Solution Approach 2:
The isolation circuit serves multiple functions: it electrically isolates the NMOS and PMOS compensation circuits to prevent interference, enables independent operation of each sense amplifier circuit, and facilitates seamless switching between compensation modes. This multi-functionality allows the isolation circuit to support the complex dual-circuit architecture without proportionally increasing overall system complexity.
Data Source
AI summary
An offset compensated sense amplifier and a memory device including the same are disclosed. A sense amplifier for sensing and amplifying data stored in a memory cell includes a first sense amplifier circuit including first and second PMOS transistors connected to a first sensing driving signal line and a second sense amplifier circuit including first and second NMOS transistors connected to a second sensing driving signal line. The sense amplifier the sense amplifier is configured to perform an offset compensation operation before sensing and amplifying the data stored in the memory cell, the offset compensation operation including a first offset compensation operation based on a threshold voltage difference between the first NMOS transistor and the second NMOS transistor, and a second offset compensation operation based on a threshold voltage difference between the first PMOS transistor and the second PMOS transistor.