Dual Read Word Line Design for Memory Power Reduction
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Solution Overview
Problem
Existing memory designs consume unnecessary power due to the need to recharge read bit lines for all bit cells in a row during read operations, even when not all cells need to be read, as a single read word line discharges all bit cells, leading to inefficient power usage.
Innovation Solution
Implementing a dual read word line design where separate read word lines are used for different subsets of bit cells within the same row, allowing only the necessary bit cells to be enabled during read operations, thereby reducing unnecessary discharging and recharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single read word line is used to access all bit cells in a row, then the read operation can access any bit cell in the row, but power is consumed to recharge read bit lines for all bit cells even when not all cells need to be read
Solution Approach 1:
The patent divides a single read word line into multiple segmented read word lines (first read word line and second read word line), where each segment is connected to a specific subset of bit cells in the row. This segmentation allows selective activation of only the necessary word line segment for the current read operation, preventing unnecessary discharge and recharge of read bit lines for other bit cells, thereby reducing power consumption while maintaining full row access capability.
2Device complexity
If a single read word line is used for all bit cells, then the design is simpler, but unnecessary discharging and recharging of read bit lines occurs
Solution Approach 1:
The read word line is segmented into multiple independent segments (first and second read word lines), each controlling a specific subset of bit cells. This segmentation enables selective activation, where only the required segment is activated during each read operation, avoiding unnecessary discharge-recharge cycles of read bit lines and reducing energy loss while maintaining manageable design complexity.
3Use of energy by moving object
If multiple read word lines are implemented for different subsets of bit cells, then power consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent segments the read word line into a manageable number of segments (first and second read word lines) that collectively cover all bit cells in the row. This segmentation reduces power consumption through selective activation while maintaining reasonable device complexity by using a limited number of segments rather than excessive division.
Solution Approach 2:
The segmented read word lines are designed to collectively provide universal access to all bit cells in the row. Each segment serves multiple bit cells within its subset, and together the segments cover the entire row, maintaining the multi-functional capability of accessing any bit cell while enabling power-saving selective activation.
Data Source
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AI summary
Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.