DRAM Data Driver Circuit Retiming for Timing Skew

The patent divides the delay adjustment function into multiple discrete delay elements (first delay element, second delay element, third delay element) that can be independently controlled. Each delay element provides a specific delay amount, and their combinations allow precise timing adjustment without requiring a complete DLL circuit. This segmentation approach achieves the required timing precision while using less silicon area than a full DLL implementation.

The patent changes the delay parameter by selecting different combinations of delay elements based on training data. The training process determines optimal delay values for different operating conditions, and these delay values are stored in lookup tables. During operation, the appropriate delay elements are activated based on the stored training data, allowing precise timing adjustment without the complexity of real-time DLL phase locking.

The patent implements a universal delay adjustment mechanism that can serve multiple DIMM slots through a single data driver circuit. The same delay elements and training process are used regardless of which DIMM slot is being accessed. The circuit adapts to different slot configurations by selecting appropriate delay values from training data, eliminating the need for separate DLL circuits for each slot and reducing overall device complexity.

Instead of implementing separate physical DLL circuits for each DIMM slot, the patent uses a single set of delay elements that are reconfigured based on training data for different slot configurations. The training process creates virtual models of the timing characteristics for each slot, and these models are used to control the shared delay elements. This copying approach allows the system to handle multiple slots with a single physical implementation, reducing complexity and cost.

The patent performs delay compensation in advance through a training process that characterizes the timing relationships between signals for different operating conditions and DIMM slot configurations. The optimal delay values are determined during training and stored in lookup tables. During normal operation, the pre-computed delay values are simply retrieved and applied, avoiding the continuous power consumption associated with active DLL phase locking and signal monitoring.

The system uses its own training data and operating patterns to automatically determine the appropriate delay settings without requiring external calibration or continuous adjustment. The lookup tables containing optimal delay values are generated from the system's own characteristics during initialization, allowing the circuit to self-adjust to different operating conditions without additional power consumption from external calibration equipment or continuous monitoring circuits.