Write Leveling Using Slower Clock Signal for Fly-By Delay
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Solution Overview
Problem
In memory systems with sequential chained topology, such as DDR3 technology, write leveling is challenging due to fly-by delays, which can lead to errors in determining the correct timing for strobe signals, especially when delays exceed the clock period, affecting throughput performance and accuracy.
Innovation Solution
A memory controller uses a slower clock signal during write leveling to accurately determine delays, with the frequency based on the maximum fly-by delay, allowing for precise synchronization of strobe signals with the rising edge of the clock signal, even when delays exceed the regular clock period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a faster clock signal is used during write leveling, then throughput performance is improved, but measurement precision of delays deteriorates
Solution Approach 1:
The system dynamically switches between two clock signals with different frequencies based on the operational phase. During write leveling calibration, a slower clock signal is used to enable accurate delay measurement. During normal write operations, a faster clock signal is used to maximize throughput performance. This dynamic frequency switching resolves the contradiction by allowing each phase to use the optimal clock frequency for its specific requirement.
Solution Approach 2:
The clock signal frequency parameter is changed based on the operational mode. The memory controller selectively applies a first clock signal with frequency F1 during write leveling and a second clock signal with frequency F2 (where F2 > F1) during write operations. This parameter change allows the system to optimize measurement precision during calibration and productivity during data operations.
2Measurement precision
If write leveling is performed with accurate delay determination, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary calibration phase using a slower clock signal that acts as a mediator between the control mechanism and the memory units. This intermediary approach simplifies the control mechanism by providing a manageable time base for delay measurement, making it easier to determine precise delays without requiring overly complex synchronization hardware.
Solution Approach 2:
Write leveling is performed as a preliminary action before normal write operations. During this preliminary calibration phase, the system uses the slower clock signal to accurately determine delays. Once calibrated, these delay values are stored and used during subsequent write operations, eliminating the need for continuous complex synchronization control during data operations.
3Measurement precision
If a slower clock signal is used during write leveling, then measurement precision is improved, but productivity during calibration decreases
Solution Approach 1:
The system applies partial action by using the slower clock signal only during the write leveling calibration phase, not during normal operations. This limited application of the slower clock signal achieves the necessary measurement precision for delay determination without permanently sacrificing productivity. The calibration phase is kept as brief as possible while still achieving accurate measurements.
Solution Approach 2:
The clock frequency is dynamically adjusted based on the operational phase - slower during calibration for precision, faster during data operations for productivity. This dynamic approach ensures that the temporary reduction in calibration speed does not impact overall system productivity, as the faster clock is immediately reinstated for actual data operations.
Data Source
AI summary
A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.