Thin Film Transistor Random Access Memory Vertical Stacking
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Solution Overview
Problem
Conventional memory devices face limitations in density, extension, and design flexibility due to the implementation of transistors across a substrate, which restricts the density of memory cells, the height dimension of memory arrays, and the arrangement of access lines.
Innovation Solution
The use of thin film transistors or vertical transistors formed above a substrate, allowing for increased density, vertical extension, and improved design flexibility in memory cell arrays by configuring transistors in multiple layers or levels above the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are implemented across a substrate, then memory devices can be manufactured with conventional processes, but the density of memory cells is restricted
Solution Approach 1:
The patent transitions from planar transistors confined to the substrate surface to three-dimensional vertical transistors that extend above the substrate. This dimensional change allows memory cells to be stacked vertically, dramatically increasing memory cell density without proportionally increasing the substrate area, thereby resolving the contradiction between density and configuration complexity.
2Length of stationary object
If transistors are implemented across a substrate, then conventional manufacturing processes can be used, but the height dimension of memory arrays is limited
Solution Approach 1:
The invention introduces vertical stacking of transistors and memory cells in the height dimension above the substrate. This enables memory arrays to extend vertically rather than only laterally, increasing the height dimension of memory arrays while maintaining compatibility with adapted conventional manufacturing processes.
3Adaptability or versatility
If transistors are implemented across a substrate, then standard transistor architectures can be used, but design flexibility in arranging access lines is restricted
Solution Approach 1:
By moving transistors to vertical configurations above the substrate, the patent frees up substrate surface area and enables more flexible routing of access lines. The vertical arrangement allows access lines to be configured in multiple planes and directions, significantly improving design flexibility for accessing memory cells compared to constrained planar layouts.
Solution Approach 2:
The vertical transistor structure segments the memory device into distinct functional layers: substrate layer, transistor active regions, gate structures, and interconnection layers. This segmentation allows independent optimization of access line arrangements in different spatial dimensions, enhancing adaptability in connecting memory cells to read/write circuits.
Data Source
AI summary
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.