RRAM Chip Segmentation for Storage and Speed Trade-offs
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Solution Overview
Problem
Existing resistive random access memory (RRAM) technologies face challenges in balancing long storage time and fast response with high computing speed, particularly due to the poor durability of RRAM with high dielectric constant resistive switching layers.
Innovation Solution
A method for manufacturing a resistive random access memory (RRAM) chip that integrates both a first-type resistive random access memory cell with a long storage time and a second-type resistive random access memory cell with fast response and high computing speed. This is achieved by using a high voltage material layer for the first-type cell and a high dielectric constant material layer for the second-type cell, allowing for distinct performance characteristics on the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high dielectric constant material layer is used as the resistive switching layer, then the response speed and computing speed are improved, but the durability and storage time deteriorate
Solution Approach 1:
The patent divides the memory chip into multiple memory units, where each unit can be independently configured with different resistive switching layer materials. This allows segmentation of the chip into regions optimized for different functions: some regions use high dielectric constant materials for fast response, while others use materials with better durability characteristics
Solution Approach 2:
The patent applies local quality by allowing different memory units or regions within the same chip to have different resistive switching layer material compositions. This enables each local region to be optimized for its specific function - fast response in compute-in-memory units and long storage time in memory units - rather than requiring uniform material properties across the entire chip
2Speed
If a high dielectric constant material layer is used as the resistive switching layer, then the computing speed is improved, but the storage time deteriorates
Solution Approach 1:
The memory chip is segmented into multiple independently configurable memory units, allowing different units to be optimized for different operations. Compute-in-memory units can use high dielectric constant materials for fast computing, while memory units can use materials with better retention characteristics for long-term storage
Solution Approach 2:
The patent creates a multi-functional memory chip that can perform both fast computing operations and long-term storage operations within the same device. By allowing different memory units to use different resistive switching layer materials, the chip achieves universal functionality for both compute-in-memory applications and persistent memory applications
3Loss of time
If the RRAM structure uses a typical sandwich MIM structure with high dielectric constant material, then the response time is reduced, but the durability deteriorates
Solution Approach 1:
The patent changes the material parameter (dielectric constant) of the resistive switching layer to optimize performance. By selecting materials with appropriate dielectric constant values and adjusting their thickness, the patent achieves fast response times while managing durability characteristics through proper material selection and structural design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The manufactured RRAM chip effectively meets both performance demands by ensuring long storage time and fast response with high computing speed, thereby overcoming the durability limitations of existing RRAM technologies.
Implementation Method 1
The resistive switching layer is usually made of a high dielectric constant (High k, HK) material such as HfOx, TaOx or TiOx. The RRAM with the HK resistive switching layer is characterized by a fast response and a high computing speed
Implementation Method 2
covering the lower interlayer dielectric layer 1, the first area lower metal layer 11, and the second area lower metal layer 12 with a barrier layer 2
Data Source
AI summary
The present disclosure provides a method for manufacturing a resistive random access memory, wherein a resistive random access memory chip manufactured thereby includes a first-type resistive random access memory cell and a second-type resistive random access memory cell, a resistive layer of the first-type resistive random access memory cell includes a high voltage material layer, and a resistive layer of the second-type resistive random access memory cell is a high dielectric constant material layer. The first-type resistive random access memory cell is characterized by a long storage time, and the second-type resistive random access memory cell characterized by a fast response and a high computing speed. The method for manufacturing a resistive random access memory has an innovative process that allows process integration of two types of resistive random access memory cells, so that the manufactured random access memory chip is able to meet two types of performance demands.