Cross-Connected Shared Bank Resources for Memory Power Optimization
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Solution Overview
Problem
Existing multi-bank memory systems are energy inefficient due to dedicated bank resources being underutilized, leading to increased power consumption and delays when refreshing rows or handling uneven read/write requests across banks.
Innovation Solution
Implementing a cross-connection mechanism that selectively connects shared bank resources across multiple banks, allowing for coincident memory bank access by sequencing row operations and sharing sense amplifiers and row buffers, thereby optimizing resource usage and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated bank resources are used for each memory bank, then each bank can independently service operations, but power consumption increases and resources remain underutilized when requests are unevenly distributed
Solution Approach 1:
The patent implements shared bank resources (sense amplifiers, row buffers) that can be dynamically allocated to serve multiple memory banks. The cross-connect switch enables a single bank resource to function for different banks based on operational needs, allowing one resource to perform multiple functions across different banks rather than each bank having dedicated resources that sit idle during uneven access patterns
Solution Approach 2:
The patent merges previously separate dedicated bank resources into shared resources that can be dynamically assigned. By combining sense amplifiers and row buffers into shared pools that serve multiple banks through cross-connect switching, the system reduces the total number of resources needed while maintaining the ability to service multiple banks independently when required
2Reliability
If dedicated bank resources are used for refreshing rows, then row refresh operations can be performed, but data must be stored back to memory cells and retrieved to row buffer, increasing operational complexity and delays
Solution Approach 1:
The patent maintains data in shared row buffers before refresh operations are needed. By keeping data preliminarily loaded in the shared row buffer, the system avoids the need to retrieve data from memory cells during the refresh operation itself, thus performing the useful action of having data ready in advance rather than retrieving it during the critical refresh timing window
Solution Approach 2:
The shared row buffer acts as an intermediary between the memory cell array and the sense amplifier during refresh operations. Instead of directly reading from and writing to memory cells during refresh, the shared row buffer mediates the operation, holding data temporarily and enabling the refresh to proceed without the delay of immediate cell access and retrieval
3Reliability
If dedicated bank resources are used, then each bank has its own sense amplifier and row buffer, but resources in one bank may be idle while another bank is overloaded
Solution Approach 1:
The patent introduces dynamic resource allocation where bank resources are not statically assigned to specific banks but can be dynamically reassigned based on real-time operational demands. The cross-connect switch enables runtime reconfiguration, allowing the system to adapt resource distribution to match actual access patterns and workload distribution across banks
Solution Approach 2:
The patent changes the operational parameter of resource allocation from fixed/dedicated to variable/sharable. By modifying how resources are assigned (from static bank ownership to dynamic sharing based on load conditions), the system optimizes resource utilization efficiency while maintaining the ability to provide independent bank operation when needed
Data Source
AI summary
Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.