Single Port Memory Concurrent Access via Dual Wordlines
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Solution Overview
Problem
Traditional memory compilers are inefficient and prone to accuracy errors in generating physical layout designs for memory circuits, particularly in handling leakage, timing, power, and noise data, and often restrict operations to a single wordline in bank architectures, limiting concurrent read and write access operations.
Innovation Solution
Implementing a dual wordline circuitry in a single port memory architecture that allows concurrent read and write operations across multiple banks using separate wordlines, enabling simultaneous operations such as reading from one bank while writing to another, with shared memory addresses and global enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory compilers analyze error prone memory instances related to entire memory circuits, then comprehensive memory analysis is achieved, but accuracy errors occur and the process becomes costly and time consuming
Solution Approach 1:
The patent segments the memory circuit analysis into individual memory instance-level analyses rather than analyzing entire memory circuits at once. The memory circuit is divided into multiple banks, each with multiple memory instances, and each instance is analyzed separately using characterized data. This segmentation eliminates accuracy errors from aggregate analysis and reduces processing time by focusing on specific instances.
Solution Approach 2:
The patent performs preliminary characterization of memory instances by analyzing characterized data (leakage, timing, power, noise) before final memory circuit design. Memory instances are pre-analyzed and evaluated using the characterized data, allowing the memory compiler to select optimal instances without time-consuming full-circuit simulations. This preliminary action improves both accuracy and efficiency.
2Productivity
If only a single wordline in one bank is accessible in bank architectures, then simple control logic is maintained, but concurrent read and write operations are limited
Solution Approach 1:
The patent segments the memory architecture into multiple banks, where each bank can independently access its own wordlines. This allows concurrent operations across banks - for example, reading from Bank 0 while writing to Bank 1 - without interfering with each other. The segmentation of banks with independent wordline control enables parallel memory access operations.
Solution Approach 2:
The patent implements a single port memory interface that can perform multiple functions concurrently through the use of multiple banks. The same memory interface can simultaneously execute read operations in one bank and write operations in another bank, providing multi-functionality without requiring separate memory ports. This universal interface handles both read and write operations across different banks concurrently.
Data Source
AI summary
Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.