Sum Address Compare Logic in Translation Lookaside Buffers
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Solution Overview
Problem
Existing methods for sum address compare operations in translation lookaside buffers (TLBs) are hindered by dependencies on carry generation paths, leading to inefficiencies and increased power consumption in processor systems.
Innovation Solution
The implementation of a sum address compare function that generates logic gate circuits with single logic gate outputs and their inversions in each memory cell, allowing for partial lookup compare operations to reduce latency and resource usage, by combining address input signals with memory cell outputs and logical operations during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an adder is utilized to generate the A+B value and then comparators are provided in a CAM to compare the A+B value with each of the CAM entries, then the sum address compare operation can be performed, but the operation is slowed by having dependencies on the carry generation path in the adder
Solution Approach 1:
The patent segments the sum address compare operation into two independent parts: (1) pre-computing partial sum values for each CAM entry during write operations, and (2) comparing these pre-computed values with the address inputs during read operations. This eliminates the need for a traditional adder with carry propagation, as each bit position can be computed independently using simple logic gates.
Solution Approach 2:
The patent performs preliminary computation of the sum values during the CAM write operation, storing these pre-computed values in the CAM alongside the address tags. During subsequent read operations, only a simple comparison is needed without any addition or carry generation, thus eliminating the speed bottleneck caused by carry propagation delays.
2Use of energy by moving object
If traditional adder and comparator circuits are used for sum address compare operations, then the function can be implemented, but power consumption increases
Solution Approach 1:
The patent replaces the mechanical adder circuit with a logical computation system. Instead of using physical adders that require carry signal propagation through multiple stages, the invention uses logic gates to compute sum bits independently based on pre-stored partial values and input addresses, significantly reducing power consumption while maintaining or improving translation efficiency.
3Measurement precision
If carry generation path dependencies are present in the adder, then accurate sum calculation is achieved, but latency increases
Solution Approach 1:
The patent computes and stores the partial sum values for each CAM entry during the write operation, so that during read operations, only a simple bitwise comparison is needed. This preliminary computation eliminates the need for real-time addition with carry propagation, reducing latency while maintaining calculation accuracy through the use of XOR gates that correctly compute sum bits without carry dependencies.
Data Source
AI summary
Techniques are described for sum address compare (A+B=K) operation for use in translation lookaside buffers and content addressable memory devices, for example. Address input signals A and B are supplied as input to the A+B=K operation and K is a previous value stored in a plurality of memory cells. In each memory cell, a single logic gate circuit output and its inversion are generated in response to updating the memory cells, wherein each single logic gate circuit has as input an associated memory cell output and a next lowest significant bit adjacent memory cell output. In each of the memory cells, a portion of the A+B=K operation associated with each memory cell is generated in a partial lookup compare circuit wherein the corresponding address input signals A and B are combined with the associated memory cell output and the generated single logic gate circuit output and its inversion during a read lookup compare operation.