Stacked Memory Bank Arrangement With Through Electrodes
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Solution Overview
Problem
Current stacked memory technologies face challenges in matching specifications with existing memory modules, particularly in parity and no-parity operations, and lack optimal refresh control methods, leading to varying bank numbers and inefficiencies in bank arrangements.
Innovation Solution
A stacked memory design that uses memory core layers with through electrodes and an interface chip for parity and no-parity operations, with address assignment and bank designation methods that maintain a constant number of banks, allowing for flexible bank arrangements and Hidden Refresh control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory chips are simply stacked one upon another, then the number of banks widely varies depending on the number of stacks, but this requires preparation of a great number of DRAM specifications for every bank number
Solution Approach 1:
The patent applies universality by designing a standardized bank arrangement where each memory chip layer contains the same number of banks (e.g., 8 banks per layer). This universal structure allows the stacked memory to maintain consistent bank numbering regardless of the number of stacked layers, eliminating the need for multiple DRAM specifications for different bank configurations.
Solution Approach 2:
The patent implements dynamics by allowing the total bank capacity to scale dynamically with the number of stacked layers while maintaining a fixed per-layer structure. The bank arrangement adapts to different stacking configurations through consistent intra-layer organization rather than changing the fundamental bank structure, enabling flexible expansion without specification proliferation.
2Quantity of substance
If DRAM chips are divided into multiple banks, then memory capacity increases, but refresh control becomes more complex in stacked structures
Solution Approach 1:
The patent applies segmentation by dividing the refresh control function into layer-specific independent control units. Each memory chip layer has its own refresh control logic that operates independently, managing only the banks within that layer. This segmented approach simplifies refresh control compared to managing all banks in the stacked structure as a single complex system.
Solution Approach 2:
The patent implements preliminary action by pre-organizing banks into layer-specific groups with dedicated refresh control logic for each layer. This preliminary organization allows each layer to be refreshed independently according to its own timing requirements, simplifying the overall refresh control architecture before the stacked memory is fully assembled and operated.
3Volume of moving object
If stacked memory is substituted for current memory modules, then miniaturization is achieved, but specifications must be changed for parity and no-parity operations
Solution Approach 1:
The patent applies local quality by implementing parity and no-parity operation modes at the interface chip level rather than requiring changes to the fundamental memory chip structure. The interface chip locally handles the specification adaptation by configuring how data is read from and written to the stacked memory layers, allowing the same physical structure to support multiple operational specifications.
Solution Approach 2:
The patent implements parameter changes by allowing the operational specifications (parity/no-parity) to be changed through configuration parameters in the interface chip rather than through physical structural changes. This enables the stacked memory to adapt to different application requirements by modifying operational parameters rather than manufacturing specifications.
Data Source
AI summary
In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.