Semiconductor Device Complementary Bit Line Pair
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving sufficient sensing margin during read operations due to inadequate amplification of signal voltages from memory cells, leading to increased consumption current, noise, and reduced sensing margins, particularly when using dummy cells with different structures and timing controls.
Innovation Solution
A semiconductor device configuration featuring complementary bit lines, memory cells, and dummy cells of the same structure, with an equalizing circuit and control circuit that manages potential storage and equalization, allowing for balanced capacitances and reduced noise by disconnecting and reconnecting cells during read operations to maintain optimal signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If dummy cells with different structures are used to balance bit line capacitances, then capacitance balance is achieved, but sensing margin is reduced due to potential deviations and noise
Solution Approach 1:
The patent employs dummy cells with the same structure as memory cells (both using 1T1C configuration) to ensure homogeneous capacitance characteristics. This homogeneity prevents potential deviations and noise generation that occur when different结构的 dummy cells are used, while still achieving capacitance balance through proper selection and control of the dummy cells.
Solution Approach 2:
The patent extracts the dummy cells from the active read operation sequence by controlling their selection timing. The dummy cells are selected during bit line equalization but kept non-selected during the actual read operation, separating their function to capacitance balancing from the signal reading function, thereby preventing them from introducing noise during sensing.
2Stability of the object's composition
If dummy cells are controlled with different timing than memory cells, then capacitance balance is improved, but reading speed decreases and consumption current increases
Solution Approach 1:
The patent performs preliminary action by selecting dummy cells during the bit line equalization phase before the actual read operation. This preliminary selection establishes the capacitance balance in advance, allowing the subsequent read operation to proceed at full speed without delays caused by capacitance imbalance corrections.
Solution Approach 2:
The patent implements periodic action through phased control of dummy cell selection. Dummy cells are selectively activated during specific periods (equalization phase) and deactivated during other periods (read operation phase), creating a rhythmic control pattern that maintains capacitance balance while preserving reading speed.
3Stability of the object's composition
If all dummy word lines are temporarily lowered to select dummy cells, then capacitance balance is achieved, but consumption current increases and noise is generated
Solution Approach 1:
The patent applies local quality by selectively activating only the specific dummy word lines corresponding to dummy cells that need capacitance balancing, rather than lowering all dummy word lines. This localized approach reduces the number of simultaneously active dummy cells, thereby reducing consumption current and minimizing noise generation while still achieving the required capacitance balance.
4Speed
If dummy cells are selected simultaneously with memory cells, then reading speed is maintained, but sensing margin decreases due to charge flow into dummy cells
Solution Approach 1:
The patent implements dynamic control by adjusting the selection timing of dummy cells relative to memory cells based on the operational phase. During bit line equalization, dummy cells are selected dynamically to balance capacitances. During the actual read operation, dummy cells are kept non-selected dynamically to prevent charge flow, while memory cells remain selected. This dynamic timing adjustment maintains reading speed while preserving sensing margin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the sensing margin and reduces noise by ensuring balanced bit line capacitances and preventing potential deviations, thereby improving read operation efficiency and reducing consumption current.
Implementation Method 1
the equalizing circuit equalizing potentials of the first and second bit lines to which the first and second dummy cells are connected
Implementation Method 2
a sense amplifier amplifying a difference in potential between the first and second bit lines
Data Source
AI summary
Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.