Resistive Memory Voltage Generation Circuit for Data Reading Accuracy

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Solution Overview

Problem

Resistive memory apparatuses face challenges in accurately reading data due to resistance state changes caused by environmental factors like temperature and time, which affect the storage material's resistance state during write operations.

Innovation Solution

A resistive memory apparatus with a voltage generating circuit that determines a read voltage code based on the switching states of memory cell pairs, applying a read voltage to accurately detect the data stored, using a voltage determination unit and path setup unit to ensure reliable data retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fixed read voltage is applied to read data from resistive memory cells, then the reading operation is simple and fast, but the resistance state changes due to temperature and time cause inaccurate data reading

Engineering Contradiction:
Improvedata reading accuracyVSAvoidvoltage generation circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic read voltage adjustment by introducing a voltage generating circuit that modifies the read voltage based on detected resistance states. The circuit includes a first voltage generating unit that provides an initial read voltage, and a second voltage generating unit that adjusts the voltage level according to feedback from the memory cell's resistance measurement, thereby maintaining reading accuracy despite environmental variations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the resistance state of the memory cell is measured during the read operation, and this measurement is fed back to the voltage generating circuit. The circuit uses this feedback information to adjust subsequent read voltages, creating a closed-loop system that compensates for resistance drift caused by temperature and time effects.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If the read voltage is adjusted to compensate for resistance state changes, then data reading accuracy is improved, but the reading operation time increases

Engineering Contradiction:
Improvedata reading accuracyVSAvoiddata reading time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a calibration or initialization phase before the actual data reading operation. During this preliminary phase, the voltage generating circuit pre-adjusts the read voltage based on initial resistance measurements or predetermined compensation values, so that when the actual data reading occurs, the voltage is already optimized and no additional adjustment time is needed during the critical read operation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If environmental factors like temperature and time are monitored to adjust read voltage, then data integrity is maintained, but the system complexity and power consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements self-service by designing the voltage generating circuit to automatically detect and compensate for resistance state changes without requiring external control or complex monitoring systems. The circuit uses the memory cell's own resistance characteristics during normal read operations to generate appropriate compensation voltages, thereby maintaining data integrity while minimizing additional power consumption and system complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9881672B2Resistive memory apparatus and voltage generating circuit therefor
Publication Date: 2018.01.30 SK HYNIX INC
  • US9881672B2 patent drawing
  • US9881672B2 patent drawing
  • US9881672B2 patent drawing

AI summary

A resistive memory apparatus may include a memory region including a plurality of resistive memory cells arranged in a plurality of memory cell pairs. The resistive memory apparatus may include a voltage generating circuit configured to generate a read voltage code based on a switching state of at least one memory cell pair. The resistive memory apparatus may include a voltage providing unit configured to generate a read voltage corresponding to the read voltage code.