Bitline Write Assist Circuitry Leakage Compensation
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Solution Overview
Problem
Conventional negative bitline write assist schemes are ineffective in preventing write failures due to leakage issues, where a floating bitline can flip polarity and fail to maintain a negative voltage, leading to incomplete write operations.
Innovation Solution
A self-compensating leakage scheme is implemented using a write driver with a gate driven higher than the Vss leakage, coupled with a capacitor providing a negative voltage supply to maintain the bitline at a low level, compensating for leakage from access transistors and ensuring successful write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional negative bitline write assist is used with a floating bitline, then write time may be extended to allow bitcell polarity flipping, but the bitline voltage rises due to leakage from unselected bitcell access transistors, column multiplexer transistors, and write driver, causing write failure
Solution Approach 1:
The patent implements a feedback mechanism where the write driver continuously monitors the bitline voltage and dynamically adjusts its drive strength to compensate for leakage current. The write driver increases its pull-down capability as the bitline voltage rises due to leakage, ensuring the bitline maintains its negative voltage level throughout the extended write operation.
Solution Approach 2:
The write driver is designed to self-adjust its operation based on the actual bitline conditions. By detecting the voltage rise caused by leakage and automatically increasing its compensatory action, the write driver serves itself to maintain write integrity without requiring external intervention or complex control logic.
2Duration of action of moving object
If the bitline is kept to Vss level through the write driver for a long duration, then the bitcell may flip polarity, but the time taken to flip is large and write assist is ineffective when DC writeability problems exist
Solution Approach 1:
The patent changes the voltage parameter of the bitline from a static Vss level to a dynamic negative voltage level that is actively maintained throughout the write operation. This parameter change enables effective write assist by ensuring the bitline remains at an appropriate voltage level even during extended write times, thereby improving write assist efficiency without sacrificing write speed.
3Reliability
If more negative voltage is applied to flip the bitcell, then write margin may be improved, but the floating bitline charges up due to leakage, making additional write time ineffective
Solution Approach 1:
The write driver employs feedback control to detect when the bitline voltage rises due to leakage and automatically increases its negative drive strength in response. This real-time adjustment ensures that the bitline maintains the necessary negative voltage level for effective write operations, extending the effective write time without requiring excessive initial negative voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates write failures by maintaining the bitline at a negative voltage, reducing leakage and ensuring successful write operations by compensating for voltage rises due to leakage, thus enhancing write assist efficiency.
Implementation Method 1
an output of a capacitor may be coupled to a gate of write driver, and when bitlines are floating, the capacitor may provide the negative voltage supply (Vss) to the gate of the write driver
Implementation Method 2
an output of a capacitor may be coupled to a gate of write driver, and when bitlines are floating, the capacitor may provide the negative voltage supply (Vss) to the gate of the write driver. This may cause the write driver to operate as a diode, and this arrangement may function as a self-compensating solution for leakage on a floating bitline
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.