Local Word Line Gating for Crossbar Memory Error Tolerance
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Solution Overview
Problem
Cross-point memory arrays face challenges in controlling and minimizing leakage currents, especially due to variations in biasing voltage and temperature, which can lead to errors and increased power consumption when multiple control lines are concurrently selected during operations like matrix multiplication.
Innovation Solution
The implementation of local word line gating units that can be programmed to disable local word lines, preventing defective memory cells from conducting and aggregating currents, thereby reducing errors and power consumption. These units can include non-volatile or volatile memory elements and analog multiplexors to manage bias voltages, and are configured to identify and mitigate defects such as shorts within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple control lines are concurrently selected during operations like matrix multiplication, then operational speed and productivity are improved, but leakage currents increase and errors occur
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, each with its own local word line gating unit. This segmentation allows selective disabling of specific segments containing defective memory cells while keeping other segments active, thereby maintaining productivity while reducing leakage currents from defective areas.
Solution Approach 2:
Local word line gating units are introduced as intermediary components between the global word lines and the memory cells. These gating units act as mediators that can selectively block or enable current flow to specific local regions, preventing leakage currents from propagating through defective memory cells while allowing legitimate operations to proceed.
2Reliability
If local word line gating units are implemented to disable defective memory cells, then error tolerance is improved, but device complexity increases
Solution Approach 1:
The patent introduces a new dimension of control by adding local word line gating units that operate at the segment level,介于global word line control and individual memory cell operation. This intermediate level of control provides fine-grained error tolerance without requiring complex per-cell control circuits, thus improving reliability while managing device complexity.
Solution Approach 2:
The system performs preliminary identification and marking of defective memory cells before normal operations. Local word line gating units are pre-configured to disable identified defective segments, so that during normal high-speed operations, the error tolerance is already in place without adding real-time complexity to the operational path.
3Loss of energy
If leakage currents are not controlled, then power consumption increases due to unnecessary current aggregation through defective memory cells
Solution Approach 1:
The patent extracts or removes the problematic current paths by disabling local word lines that connect to defective memory cells. By taking out the defective segments from the active circuit, the system prevents leakage currents from flowing through these paths, thereby reducing power consumption while maintaining ease of operation through automated gating control.
Data Source
AI summary
Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.