Memory Controller Clock Activation Circuit for Power Reduction
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Solution Overview
Problem
In semiconductor memory devices like DRAMs, the use of a system clock for synchronizing data transmission leads to increased power consumption and timing margin reduction due to intersymbol interference in data strobe signals, while relying solely on the system clock for synchronization can be power-intensive.
Innovation Solution
A memory device and method that utilize a first clock for command operations and a second, passed-through version of the system clock for data operations, activated and deactivated based on specific commands like Active, Bank Active, Write, or Read, and Precharge, to optimize clock usage and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system clock is used for synchronizing data transmission, then synchronization is achieved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling the second clock (data clock) only during specific data transmission periods and disabling it during idle periods. The clock activation circuit generates enable/disable signals based on command detection, creating a periodic on-off pattern that maintains synchronization when needed while reducing power consumption during non-data periods.
Solution Approach 2:
The patent implements dynamics by making the second clock dynamic rather than continuous. The clock signal transitions between active and inactive states based on operational requirements, with the clock activation circuit dynamically controlling clock enablement during data transmission and disabling during idle periods, adapting power usage to actual needs.
2Productivity
If the data strobe signal is used for data transmission, then data transmission is achieved, but timing margin is reduced due to intersymbol interference
Solution Approach 1:
The patent introduces an intermediary second clock signal that is derived from but distinct from the system clock. This intermediary clock is used specifically for data transmission timing, separating the data clocking function from the command clocking function and eliminating the intersymbol interference issues that affect data strobe signals while maintaining reliable timing margins.
3Reliability
If the system clock is continuously activated, then synchronization is maintained, but unnecessary power consumption occurs
Solution Approach 1:
The patent applies periodic action by enabling the second clock (data clock) only during specific data transmission periods and disabling it during idle periods. The clock activation circuit generates enable/disable signals based on command detection, creating a periodic on-off pattern that maintains synchronization when needed while reducing power consumption during non-data periods.
Solution Approach 2:
The patent extracts the data clocking function from the continuous system clock by creating a separate second clock that is activated only when needed for data transmission. This extraction allows the system to maintain the primary system clock for commands while removing unnecessary clock activation for data operations, eliminating wasted energy.
Data Source
AI summary
A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.