Memory Device Spacer Layer Protection Method

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Solution Overview

Problem

Current manufacturing methods for semiconductor memory devices, such as MRAM, face challenges in protecting memory units during processing, leading to reduced manufacturing yield and potential damage to the memory devices.

Innovation Solution

A manufacturing method involving the formation of a conformal spacer layer and a non-conformal spacer layer on memory units, where the non-conformal spacer layer has overhang structures that increase spacer material on the sidewalls, enhancing protection and yield by maintaining more spacer material during subsequent etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conformal spacer layer is formed on memory units, then the memory units are protected during subsequent processing, but the protection is insufficient leading to reduced manufacturing yield

Engineering Contradiction:
Improvemanufacturing yieldVSAvoiddamage to memory units during processing
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The spacer layer is divided into two distinct portions: a conformal spacer layer that provides baseline protection, and a non-conformal spacer layer with overhang structures that provides enhanced protection. This segmentation allows each layer to perform its specific protective function, with the non-conformal layer specifically addressing the insufficient protection issue by adding extra spacer material on sidewalls to prevent damage during etching processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The non-conformal spacer layer introduces a new dimensional aspect by forming overhang structures that extend beyond the conformal layer's coverage. This additional dimension (overhang) provides extra spacer material on the sidewalls of memory units, creating a more comprehensive protective barrier that prevents damage during subsequent processing steps and improves manufacturing yield.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If more spacer material is added on sidewalls, then protection of memory units is enhanced, but the complexity of the manufacturing process increases

Engineering Contradiction:
Improveprotection of memory unitsVSAvoidspacer layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The spacer layer is segmented into conformal and non-conformal portions, each formed in separate deposition steps. This segmentation allows the complex non-conformal layer with overhang structures to be built systematically on top of the conformal layer, making the overall process manageable while achieving enhanced protection through the combined structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conformal spacer layer is formed first as a preliminary protective layer, establishing a baseline protection before the non-conformal layer is added. This preliminary action ensures that the memory units are already protected during initial processing, and the subsequent non-conformal layer can be deposited to provide additional overhang protection without requiring complete process redesign.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240032434A1Manufacturing method of memory device
Publication Date: 2024.01.25 UNITED MICROELECTRONICS CORP
  • US20240032434A1 patent drawing
  • US20240032434A1 patent drawing
  • US20240032434A1 patent drawing

AI summary

A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.