Hybrid Write-Assist SRAM Cell Voltage Droop and Negative Bit Line
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Solution Overview
Problem
The reduction of SRAM core voltage has lagged behind logic voltage, limiting semiconductor chip power consumption improvement due to increased threshold voltage variations and SRAM capacity requirements, leading to write failure issues in SRAM cells.
Innovation Solution
A hybrid write-assist memory system that employs a separable cell supply voltage reduction and negative bit line voltage during write operations, utilizing a supply voltage droop unit and negative bit line unit to enhance write assist capabilities without increasing layout area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If write assist circuits are introduced to reduce minimum voltage, then voltage reduction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the write assist function into two distinct units: a supply voltage droop unit that reduces the separable cell supply voltage, and a negative bit line unit that drives the bit line negative. This segmentation allows each unit to be optimized independently and simplifies the overall implementation compared to a monolithic write assist circuit.
Solution Approach 2:
The supply voltage droop unit utilizes the existing bit line precharge capacitance to generate the voltage reduction effect. During the write operation, when the bit line is discharged, the capacitance automatically creates a voltage droop that reduces the SRAM cell supply voltage, eliminating the need for separate active voltage regulation circuitry.
2Reliability
If separable cell supply voltage reduction is applied, then write operation reliability is improved, but control complexity increases
Solution Approach 1:
The separable cell supply voltage is precharged to match the array supply voltage before the write operation begins. The voltage reduction is then automatically triggered during the write operation when the bit line is discharged, eliminating the need for complex real-time voltage control logic.
Solution Approach 2:
The supply voltage droop unit is controlled by the bit line precharge signal, which provides feedback about the write operation state. When the bit line precharge signal indicates that the bit line will be discharged during write, the droop unit activates to reduce the separable cell supply voltage accordingly.
3Reliability
If negative bit line voltage is applied concurrently with voltage reduction, then write assist effectiveness is improved, but power consumption increases
Solution Approach 1:
The negative bit line voltage is applied periodically only during the write operation when needed, rather than continuously. The bit line is precharged to a positive voltage during read operations, and only discharged to a negative voltage during write operations, reducing overall power consumption while maintaining write assist effectiveness.
Data Source
AI summary
A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.