Multi-Level Dynamic Memory Device With Adjustable Correction Capacitors
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Solution Overview
Problem
Conventional multi-level dynamic memory devices face reduced sensing margins due to varying capacitance of coupling capacitors, which affects the accuracy of memory cell restoration, especially with advancements in cell capacitor manufacturing where the capacitance approaches that of the bit line.
Innovation Solution
Incorporation of MOS-type correction capacitors connected in parallel to the coupling capacitors, with capacitance adjusted by a control voltage signal, and the use of dummy memory cells to enhance the restoring operation, ensuring accurate capacitance ratios and reduced errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance of coupling capacitors is increased to improve restoration accuracy, then the sensing margin for '10' increases, but the sensing margin for '11' decreases
Solution Approach 1:
The patent applies dynamics by making the coupling capacitor capacitance adjustable rather than fixed. A control voltage signal dynamically changes the capacitance value to optimize both '10' and '11' sensing margins under different operating conditions, resolving the trade-off between restoration accuracy and sensing margin
Solution Approach 2:
The patent changes the capacitance parameter of the coupling capacitors by applying a control voltage signal that adjusts the capacitance value. This parameter change allows the system to adapt to different restoration requirements while maintaining adequate sensing margins for both data states
2Manufacturing precision
If the capacitance of cell capacitor increases to become comparable with bit line capacitance, then manufacturing precision improves, but the sensing margin is reduced due to inability to ignore cell capacitor capacitance in calculations
Solution Approach 1:
The patent addresses the increased cell capacitor capacitance by dynamically adjusting the coupling capacitor capacitance through a control voltage signal. This compensates for the previously negligible cell capacitor capacitance now becoming significant, maintaining accurate restoration while preserving sensing margins
3Measurement precision
If the lengths of main bit line pair and sub-bit line pair are set in 2:1 relationship to achieve accurate restoration, then restoration accuracy improves, but the design complexity increases when cell capacitor capacitance cannot be ignored
Solution Approach 1:
The patent simplifies the design by using a control voltage signal to adjust coupling capacitor capacitance, eliminating the need for complex bit line length ratio calculations that must account for cell capacitor capacitance. This dynamic parameter adjustment reduces design complexity while maintaining restoration accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution maintains a consistent charge flow between bit lines and reduces restoring errors, thereby increasing the sensing margin and improving the accuracy of memory cell operations.
Implementation Method 1
first and second correction capacitors, connected in parallel to the first and second coupling capacitors, respectively, and having a capacitance adjusted by a control voltage signal
Data Source
AI summary
A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.