Input-Output Circuit for MISR Function in Memory Devices

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Solution Overview

Problem

The design of high bandwidth memory (HBM) systems faces increased design burdens due to the need for additional circuits and timing adjustments for the multiple-input shift register (MISR) function, which complicates the integration of MISR circuits and affects the reliability of test results.

Innovation Solution

An input-output circuit that operates in both normal and test write modes using the same timing conditions, incorporating a reception circuit and a register circuit synchronized with a clock signal and a delayed test clock signal to efficiently perform the MISR function without additional timing adjustments, and filters command-address signals to enhance test result reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional circuits are added to support MISR function, then MISR functionality is achieved, but device complexity increases

Engineering Contradiction:

ImproveMISR function supportVSAvoiddesign overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The input-output circuit is designed to perform both normal write operations and MISR test operations using the same hardware resources. The reception circuit and register circuit can operate in either normal mode or test mode, eliminating the need for separate dedicated MISR circuits and reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If independent timing adjustment is made for test operation, then test reliability is improved, but device complexity increases

Engineering Contradiction:

Improvetest result reliabilityVSAvoidtiming adjustment complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the timing control for normal write operations and test operations into a unified system. The same clock signal and control logic are used for both modes, eliminating the need for separate timing adjustment mechanisms and reducing design complexity while maintaining test reliability through proper mode switching.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9959935B2Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same

Publication Date: 2018.05.01 SAMSUNG ELECTRONICS CO LTD

AI summary

An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.