Address Decoder Permanent Fault Detection in Memory Devices

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Solution Overview

Problem

Existing methods for detecting faults in electronic memory devices, particularly permanent faults in address decoders, are inadequate as they cannot distinguish between faults in the memory array and address decoders, and do not effectively detect permanent faults in these components.

Innovation Solution

A method involving an ECC module and a test module that writes and reads specific words at designated addresses to identify permanent faults by comparing preliminary and comparison words, and using excitation addresses to detect faults through logical and physical address variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If existing fault detection methods are used, then general error detection is possible, but permanent faults in address decoders cannot be distinguished from memory array faults

Engineering Contradiction:
Improvefault detection precisionVSAvoiddifficulty of detecting permanent faults
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The fault detection process is segmented into distinct phases: preliminary word writing, excitation address writing, comparison word reading, and fault analysis. By dividing the detection process into separate stages with specific operations at each stage, the method can isolate and identify permanent faults in address decoders distinct from memory array faults.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method performs preliminary actions by writing preliminary words to preliminary addresses before performing the actual fault detection. This preliminary operation prepares the system state and allows subsequent comparison operations to identify permanent faults that would otherwise be indistinguishable from temporary errors or memory array faults.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive fault detection is performed, then detection accuracy improves, but the complexity of the detection method increases

Engineering Contradiction:
Improvememory device reliabilityVSAvoiddetection method complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test module is designed to perform multiple functions: writing preliminary words, writing excitation addresses, reading comparison words, and analyzing faults. This multi-functional approach consolidates what would otherwise require separate dedicated circuits for each detection task, maintaining reliability while managing system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The method introduces intermediary elements including preliminary words, excitation addresses, and comparison words that mediate between the test module and the memory system. These intermediaries enable indirect detection of permanent faults through comparison operations, achieving high reliability without requiring direct observation of decoder internal states.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9312028B2Method for detecting permanent faults of an address decoder of an electronic memory device
Publication Date: 2016.04.12 STMICROELECTRONICS SRL
  • US9312028B2 patent drawing
  • US9312028B2 patent drawing
  • US9312028B2 patent drawing

AI summary

An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address.