Digital Storage TRIZ Cases

Multi-level bias generator interpolates intermediate outputs between boundary condition outputs to supply precise control signals.

A ferroelectric tunnel junction stores binary or analog data by controlling the domain structure of a thin ferroelectric layer through applied voltages.

A test device connects a resistor to an SRAM bit line to form a source follower circuit for measuring transistor characteristics.

A write tracking circuit uses a dummy memory cell and delay unit to generate accurate feedback signals.

Segmented bit lines with parallel bypass paths isolate sneak currents in RRAM arrays, reducing errors without increasing device complexity.

A semiconductor memory device uses a code controller to generate control signals for selective latching of Mode Register Set codes.

Edge blocks balance sense amplifier loads, reducing wasted layout area in small AI memory.

A ferroelectric memory cell rewrites its logic state periodically to counteract domain shifting and preserve data integrity.

A semiconductor memory sensing architecture uses a delay circuit to activate a reference cell before data selection.

A tri-state logic enable circuit temporarily stores address signals and outputs synchronized enable pulses to selected memory banks.

A non-volatile latch circuit stores device configurations using chalcogenide memory elements and cross-coupled CMOS inverters.

Auxiliary driver bypasses delay for first strobe signal to align timing with system clock edges.

A bit line sense amplifier electrically separates from input/output lines to minimize load effects during data masking operations.

A data transmission circuit adjusts sense amplifier enable signal pulse width based on input data swing width to secure timing margins.

Variable pulse width encoding simplifies programming complexity while maintaining precise control over multiple resistance states in phase change memory cells.

A storage controller adjusts write energy in resistance random access memory to store data for specific holding periods.

Transpose cells multiply weights by inputs without write disturb, increasing sensing margin and reducing energy.

A controller manages non-volatile memory power removal by detecting and suspending active background operations before supply voltage drops.

Parallel ferroelectric memory cells execute multiply-accumulate operations directly within the neural network device architecture.

A precharge voltage supply unit dynamically switches between standby and active internal voltages to optimize input/output line charging.

A non-volatile SRAM cell transfers data to magnetic tunnel junction nodes during standby mode.

A PCM-based neural network device shares backward spike generators across output layer neurons to minimize circuit area and energy consumption.

A memory device uses a selector with variable electrical parameters to control access to memory units.

Pre-sense amplifiers divide power supply voltage to stabilize reference potentials, preventing load-induced errors during semiconductor memory read operations.

Integrated equalizer driver boosts signal sharpness by compensating for channel distortion without dedicated control circuitry.

Vertical stacking with through-silicon vias increases prefetch bandwidth without expanding chip area.

A row address comparator integrates voltage level shifting and latching to compare addresses across domains.

Differential magnetic tunnel junction elements use reversed layer orders to enable same-polarity current writing.

A memory apparatus autonomously detects and repairs fail word lines using a fuse array and rupture operation unit.

An intermediary PMOS circuit equalizes bit line potentials, mitigating capacitive coupling interference and ground bounce on long signal lines.

A semiconductor capacitor uses a switching element to accumulate charge within a dielectric layer for reliable data storage.

Dynamic dead zone adjustment stabilizes internal voltage levels, reducing pull-down times and preventing data determination errors in memory circuits.

Extending the postamble section prevents glitches in the high impedance state, maintaining data window margin and enabling reliable high-speed operations.

An adaptive calibration scheduling method adjusts memory subsystem timing based on eye opening width and reference voltage scores.

Dual etch stop layers protect ovonic threshold switch materials from fluorine plasma damage during patterning, preventing leakage current increases.

A protective resistance film with 1–100 Ω·cm resistivity connects in series with memory cells to suppress operation current during simultaneous access.

Variable access paths in multi-port semiconductor memory devices reduce test time by routing all memory areas through a single designated test port.

Segmented reference word lines isolate write disturb effects while folded bit lines convert noise into differential signals for reliable sensing operations.

A semiconductor device design reduces power consumption by transmitting only one frequency-divided clock signal during write operations.

A memory bypass circuit enables concurrent read and write operations without accessing the memory array.

A resistive memory control block varies reference values based on digital code analysis to discriminate data states.

A memory element transitions between high and low current states using partial reset signals to create intermediate conductivity levels.

Asynchronous access establishes a known logic state to enable polarity-consistent programming pulses in multi-level memory cells.

An internal synchronization circuit shifts single data rate signals to simulate double data rate operations, resolving miniaturization reliability issues.

Segmented memory arrays apply tailored switching currents to prevent Joule heating and back hopping during data writing.

Segmenting detection into preliminary writing, excitation addressing, and comparison phases isolates permanent decoder faults from memory array errors.

A shared test signal line connects multiple input output terminals to a calibration circuit for independent characteristic adjustment.