Integrated Row Address Comparator for Memory Redundancy

Solution Overview

Problem

In memory designs, implementing row redundancy and dual voltage domains increases circuit complexity and size due to the need for multiple voltage level shifters, which also introduces delays and power consumption issues.

Innovation Solution

A row address comparator with integrated voltage level shifting and latching functionality, which compares row addresses in a single voltage domain and outputs match signals in a different domain, reducing the need for additional voltage level shifters and minimizing downstream latching delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple voltage level shifters are used to support row redundancy and dual voltage domains, then reliability is improved, but device complexity and chip area increase

Engineering Contradiction:

Improvememory failure preventionVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the voltage level shifting function with the address comparison function into a single integrated circuit block. The row address comparator simultaneously compares addresses and performs voltage level shifting, eliminating the need for separate voltage level shifter components and reducing overall circuit complexity while maintaining the dual voltage domain capability needed for reliability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The row address comparator is designed to perform multiple functions: address comparison, voltage level shifting, and signal latching. This multi-functional design reduces the total number of components needed in the memory system, as the same circuit block that ensures reliable address matching also handles voltage domain translation

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple voltage level shifters are used to support row redundancy and dual voltage domains, then reliability is improved, but chip area increases

Engineering Contradiction:

Improvememory failure preventionVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the voltage level shifting function with the address comparison function into a single integrated circuit block. The row address comparator simultaneously compares addresses and performs voltage level shifting, eliminating the need for separate voltage level shifter components and reducing overall circuit complexity while maintaining the dual voltage domain capability needed for reliability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The row address comparator is designed to perform multiple functions: address comparison, voltage level shifting, and signal latching. This multi-functional design reduces the total number of components needed in the memory system, as the same circuit block that ensures reliable address matching also handles voltage domain translation

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple voltage level shifters are used in the data path, then dual voltage domain operation is enabled, but delays and setup time increase

Engineering Contradiction:

Improvevoltage domain operationVSAvoidaddress pin setup time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent combines the voltage level shifting function with the address comparison function into a single integrated circuit block. The row address comparator simultaneously compares addresses and performs voltage level shifting, eliminating the need for separate voltage level shifter components and reducing overall circuit complexity while maintaining the dual voltage domain capability needed for reliability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated row address comparator performs voltage level shifting in advance as part of the address comparison process, rather than as a separate subsequent step. This preliminary integration of voltage domain translation into the comparison logic reduces the overall timing delay and setup time required for address pin operations

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11302415B2Row address comparator for a row redundancy control circuit in a memory

Publication Date: 2022.04.12 MARVELL ASIA PTE LTD

AI summary

Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.