In-Memory Computing Circuit With Parallel Ferroelectric Memories
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Solution Overview
Problem
Current neural network devices face inefficiencies due to the separation of computational units and memory in traditional digital computers, leading to excessive time and power consumption during data transmission and processing, particularly in performing multiply-accumulate operations.
Innovation Solution
The implementation of an in-memory computing circuit with a neural network device that includes a plurality of memory cells, each comprising at least two ferroelectric memories connected in parallel along a word line, allowing for linear state-change characteristics and efficient weight updates, thereby reducing power consumption and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional digital computer architecture with separated computational units and memory is used, then device complexity is reduced, but power consumption increases and processing speed decreases due to excessive data transmission time
Solution Approach 1:
The patent merges memory and computation by implementing in-memory computing circuits where ferroelectric memory cells directly perform neural network operations. The memory cells are configured to execute multiply-accumulate operations without data transmission to separate computational units, thereby reducing power consumption while accepting increased device complexity.
2Device complexity
If traditional digital computer architecture with separated computational units and memory is used, then device complexity is reduced, but processing speed decreases due to excessive data transmission time
Solution Approach 1:
The patent merges memory and computation by implementing in-memory computing circuits where ferroelectric memory cells directly perform neural network operations. The memory cells are configured to execute multiply-accumulate operations without data transmission to separate computational units, thereby increasing processing speed while accepting increased device complexity.
3Measurement precision
If in-memory computing circuit with parallel ferroelectric memories is implemented, then weight update precision is improved, but device complexity increases
Solution Approach 1:
The patent segments each memory cell into multiple parallel ferroelectric memory units (first and second ferroelectric memories). This segmentation enables independent weight storage and computation operations within each cell, improving weight update precision through differential processing while distributing circuit complexity across multiple simple parallel units rather than a single complex unit.
4Use of energy by moving object
If in-memory computing circuit with parallel ferroelectric memories is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges memory and computation by implementing in-memory computing circuits where ferroelectric memory cells directly perform neural network operations. The memory cells are configured to execute multiply-accumulate operations without data transmission to separate computational units, thereby reducing power consumption while accepting increased device complexity.
Solution Approach 2:
The ferroelectric memory cells perform computation operations autonomously within the memory array itself. The in-memory computing circuit enables weights to be updated directly in place without requiring external computational units, allowing the system to serve itself and reduce power consumption despite increased circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables more precise and accurate weight updates with reduced power consumption, enhancing the performance and efficiency of neural network operations by integrating memory and computation within the neural network device.
Implementation Method 1
each of the plurality of memory cells comprises at least two ferroelectric memories connected in parallel along a corresponding word line
Data Source
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AI summary
Provided is a neural network device including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells arranged at points where the plurality of word lines and the plurality of bit lines intersect one another. Each of the plurality of memory cells includes at least two ferroelectric memories connected in parallel along a word line corresponding to each of the plurality of memory cells.