Internal Synchronization Circuit for DDR Memory Testing
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Solution Overview
Problem
Miniaturization of memory devices like DRAM has made them more prone to damage, making pre-packaging testing challenging, and existing testing methods may not adequately test DDR operations due to limitations in providing command and address signals at high speeds, potentially leading to undetected defects.
Innovation Solution
Incorporating an internal synchronization circuit that delays and shifts SDR signals to simulate DDR operations, allowing for proper latching of commands and addresses on both rising and falling edges of the clock signal, enabling comprehensive testing of DDR memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If memory devices are miniaturized to reduce size, then device dimensions are reduced, but susceptibility to damage increases
Solution Approach 1:
The patent performs testing operations on the memory device before final packaging. By conducting read and write operations at anticipated operating conditions prior to packaging, the system identifies defective devices early, preventing damaged or unreliable miniaturized devices from being shipped to customers.
2Measurement precision
If testing is performed at high speeds to simulate DDR operations, then testing accuracy improves, but testing throughput decreases
Solution Approach 1:
The patent dynamically adjusts the clock signal frequency during testing. The system can operate at different clock frequencies depending on the specific test being performed, allowing high-speed testing when accuracy is critical while maintaining overall testing efficiency through flexible frequency management.
Solution Approach 2:
The patent changes operating parameters including clock frequency and data rate during testing. By varying these parameters to match anticipated customer operating conditions, the system achieves accurate simulation of DDR operations while managing testing throughput through parameter optimization.
3Ease of operation
If command and address signals are provided at SDR rate, then ease of operation improves, but ability to test DDR operations deteriorates
Solution Approach 1:
The patent uses an intermediary mechanism where the testing system provides commands and addresses at SDR rate through external pads, but internally generates DDR-rate clock signals and synchronizes the signal processing. This intermediary approach allows easy external signal provision while achieving accurate DDR operation testing internally through synchronous circuitry that processes signals at the higher DDR rate.
Data Source
AI summary
In some examples, a memory device may include an internal synchronization circuit that provides for double data rate operation of the memory device when external single data rate signals are provided to the memory device. The external signals may be command and/or address signals provided by an external testing circuits in some examples. The internal synchronization circuit may latch and/or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.