Shared Test Signal Line for I/O Terminal Calibration

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Solution Overview

Problem

Conventional semiconductor apparatuses face challenges in optimizing input/output terminal characteristics due to differences in off-chip architecture and PVT variations, leading to increased circuit area and design complexities from the need for numerous independent signal lines for calibration.

Innovation Solution

An input/output terminal characteristic calibration circuit that uses a shared test signal line to calibrate characteristics of multiple terminals, allowing for independent calibration of selected terminals through a common connection, reducing the number of signal lines required and simplifying circuit design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If independent signal line sets are used to connect each input/output terminal to the characteristic calibration signal generation circuit, then each terminal can be calibrated independently, but the circuit area increases and design complexity increases

Engineering Contradiction:
Improveindependent calibration capabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple independent signal line sets into a shared signal line that is time-multiplexed to serve multiple input/output terminals. Instead of providing separate calibration signal paths for each terminal, a single signal line is shared across all terminals through sequential activation, thereby reducing circuit area while maintaining independent calibration capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic control mechanisms including a test mode signal generator and a selector circuit that dynamically route the calibration signal to different terminals based on test mode activation. This dynamic switching allows a static shared signal line to serve multiple terminals sequentially, resolving the contradiction between area reduction and independent calibration.

Inventive Principle:
Principle #15Dynamics

2Reliability

If independent signal line sets are used to connect each input/output terminal to the characteristic calibration signal generation circuit, then each terminal can be calibrated independently, but design complexity increases

Engineering Contradiction:
Improveindependent calibration capabilityVSAvoidsignal line arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple calibration signal transmission paths into a single shared signal line, dramatically simplifying the signal line arrangement. Instead of managing numerous independent signal lines for each terminal, the design uses one shared line controlled by dynamic routing, reducing design complexity while preserving independent calibration functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared signal line is designed to serve multiple functions: it can transmit calibration signals to any of the input/output terminals sequentially through dynamic control. This multi-functional approach eliminates the need for dedicated signal lines for each terminal, thereby simplifying the overall signal line arrangement and reducing design complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If the number of operation characteristic-related items is increased, then calibration precision improves, but the number of signal lines increases and circuit area increases

Engineering Contradiction:
Improvecalibration precisionVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent implements periodic action by sequentially activating different input/output terminals for calibration through a test mode signal generator. Each terminal is calibrated in turn through the shared signal line, allowing multiple calibration parameters to be tested and adjusted over time without requiring simultaneous signal lines for all parameters, thus maintaining calibration precision while minimizing circuit area.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10622086B2Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same
Publication Date: 2020.04.14 SK HYNIX INC
  • US10622086B2 patent drawing
  • US10622086B2 patent drawing
  • US10622086B2 patent drawing

AI summary

An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.