Non-volatile SEU Tolerant Latch Using Chalcogenide Memory
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Solution Overview
Problem
Memory devices, such as SRAMs and FPGAs, are susceptible to single-event upsets (SEUs) in high-radiation environments like satellite orbital space, leading to unreliable data storage due to electron-hole pairs generated by energetic particles, and existing non-volatile solutions like flash memories are not radiation tolerant.
Innovation Solution
A non-volatile single-event upset (SEU) tolerant latch circuit is designed using cross-coupled CMOS inverters with feedback resistors and chalcogenide memory elements, allowing for the storage and retrieval of device configurations, making the system immune to SEUs by utilizing the phase transformation properties of chalcogenide materials like germanium, antimony, and tellurium.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile SRAM cells are used to store device configurations, then fast access and re-programmability are achieved, but radiation tolerance and data retention are lost
Solution Approach 1:
The configuration storage system is segmented into two distinct parts: volatile SRAM cells for fast access during operation and chalcogenide memory elements for radiation-tolerant retention. This segmentation allows each component to optimize its specific function without compromise.
Solution Approach 2:
Device configurations are pre-loaded into chalcogenide memory elements before radiation exposure occurs. These elements retain the configuration data even when subjected to radiation, serving as a preliminary backup that can restore the SRAM state if upset occurs.
2Duration of action of stationary object
If flash memories are used for non-volatile configuration storage, then data retention is improved, but radiation tolerance and re-programmability are worsened
Solution Approach 1:
The patent changes the material parameter of the memory element from conventional flash memory materials to chalcogenide materials (such as germanium, antimony, and tellurium), which have fundamentally different radiation tolerance characteristics while maintaining non-volatile storage capabilities.
Solution Approach 2:
The invention uses composite memory architecture combining chalcogenide materials with standard CMOS circuitry, creating a hybrid system that leverages the radiation tolerance of chalcogenides and the成熟 technology of CMOS for a robust non-volatile configuration storage solution.
3Ease of manufacture
If standard CMOS circuits are used in high-radiation environments, then manufacturing simplicity is maintained, but single-event upset susceptibility increases
Solution Approach 1:
Chalcogenide memory elements serve as an intermediary between the volatile SRAM and the external configuration source. They absorb the radiation impact and provide a stable, retentive storage layer that protects the SRAM from single-event upsets while maintaining compatibility with CMOS manufacturing.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the memory storage medium by introducing chalcogenide materials, which have different radiation interaction properties than standard silicon-based memory, thereby reducing single-event upset susceptibility while remaining manufacturable with existing semiconductor processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a reliable and radiation-tolerant storage mechanism for device configurations, ensuring data integrity across power cycles and reducing the likelihood of SEUs in high-radiation environments, thereby enhancing the reliability of memory devices in space applications.
Implementation Method 1
making the system immune to SEUs by utilizing the phase transformation properties of chalcogenide materials like germanium, antimony, and tellurium
Implementation Method 2
The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor.
Data Source
AI summary
A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.