Memory Unit for Multi-Bit CNN Computing-In-Memory Applications
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Solution Overview
Problem
Current memory units for multi-bit convolutional neural network (CNN) based computing-in-memory (CIM) applications face challenges such as write disturb issues, threshold voltage variations, small sensing margins, and high input precision requirements, which hinder energy efficiency and area savings.
Innovation Solution
A memory unit and array structure controlled by a first and second word line, incorporating memory cells and transpose cells that allow for multi-bit input values to be multiplied by weights, generating output values without causing write disturb and reducing threshold voltage variations, while enabling efficient energy and area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of word lines are turned on at the same time to improve computing speed, then productivity is improved, but write disturb issue occurs and reliability deteriorates
Solution Approach 1:
The patent segments the memory array into multiple independent blocks, each with its own word lines. This allows selective activation of specific blocks during computing operations, enabling parallel processing while limiting the total number of simultaneously active word lines to avoid write disturb effects.
2Area of stationary object
If multi-level sensing is performed to increase memory density, then area is reduced, but sensing margin becomes small and measurement precision deteriorates
Solution Approach 1:
The patent transitions from in-plane sensing to out-of-plane sensing by utilizing the vertical dimension of magnetoresistive devices. This allows multi-level data storage and sensing without compromising the sensing margin, as the out-of-plane magnetization switching provides distinct resistance states that are easier to distinguish.
3Measurement precision
If high input precision is used to improve computation accuracy, then measurement precision is improved, but device complexity increases and area expands
Solution Approach 1:
The patent replaces complex electronic sensing and readout circuits with a magnetic field-based computing mechanism. The magnetoresistive devices perform computing operations through magnetic field interactions, eliminating the need for complex electronic circuitry while maintaining high computation precision.
4Reliability
If threshold voltage variations are reduced to improve computation yield, then reliability is improved, but manufacturing precision requirements increase and cost rises
Solution Approach 1:
The patent changes the fundamental operating parameter from electrical threshold voltage to magnetic switching field. This eliminates sensitivity to threshold voltage variations and their impact on computation yield, as magnetic switching is determined by the applied magnetic field rather than device-specific voltage thresholds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the simultaneous activation of multiple word lines without write disturb, increases sensing margin, and reduces energy and area requirements, enhancing the performance and efficiency of multi-bit CNN based CIM applications.
Implementation Method 1
a magnetoresistive device comprising a first electrode, a second electrode, a magnetic tunnel barrier sandwiched between the first electrode and the second electrode, and a cap layer on the magnetic tunnel barrier
Implementation Method 2
a magnetic field generation unit configured to generate a magnetic field in a first direction along a first axis parallel to the substrate
Implementation Method 3
a readout unit configured to sense a resistance of the magnetoresistive device
Data Source
AI summary
A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.