Write Tracking Circuit for SRAM Low Voltage Reliability
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Solution Overview
Problem
Existing write tracking circuits in SRAMs fail to provide accurate feedback at low supply voltages, leading to timing inconsistencies and reduced yield due to process, voltage, and temperature variations, causing write operations to fail and resulting in incorrect feedback signals that deadlock the clock generation module.
Innovation Solution
A novel write tracking circuit is introduced, featuring a dummy memory cell coupled with a delay unit and logic operation units, generating a write feedback signal based on logic operations between signals on the dummy word line and bit lines, ensuring correct feedback even under minimum operating voltage conditions by using a series of CMOS standard inverters and a test unit to determine write operation failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write tracking circuit uses conventional structure without delay unit, then circuit complexity is reduced, but feedback signal becomes incorrect when write operation fails at low voltages
Solution Approach 1:
The delay unit acts as an intermediary component between the dummy memory cell and the feedback signal generation logic. It introduces a controlled time delay that allows the feedback signal to be generated correctly even when the write operation to the dummy cell fails, thereby resolving the contradiction between reliability and complexity
Solution Approach 2:
The delay unit performs a preliminary action by introducing a time delay before the feedback signal is generated. This preliminary delay ensures that the feedback logic has sufficient time to correctly interpret the write operation status, preventing incorrect feedback even when write fails at low voltages
2Measurement precision
If write tracking circuit does not consider data write delay, then circuit operation is simplified, but timing accuracy deteriorates at low supply voltages
Solution Approach 1:
The write tracking circuit implements a feedback mechanism where the delay unit provides timing information back to the feedback logic. This feedback loop allows the circuit to automatically adjust timing parameters based on the actual write operation duration, improving timing accuracy without requiring complex external control mechanisms
Solution Approach 2:
The delay unit enables the circuit to self-adjust timing parameters by internally measuring the write operation duration and using this information to generate accurate feedback signals. The circuit serves itself by automatically compensating for timing variations at low voltages without external intervention
3Use of energy by moving object
If SRAM operates at lower supply voltage to reduce power consumption, then power efficiency improves, but write speed decreases causing write operation failures
Solution Approach 1:
The circuit uses a dummy memory cell that copies the essential timing characteristics of the actual memory cell without requiring it to perform the actual write operation. By measuring the write delay on the dummy cell, the circuit can determine correct feedback timing even when the real cell fails to write successfully at low voltages
Solution Approach 2:
The delay unit performs a preliminary measurement of the write operation timing on the dummy cell before generating the feedback signal. This preliminary timing measurement allows the circuit to compensate for the reduced write speed at low voltages and generate accurate feedback even when the write operation fails
Data Source
AI summary
A write tracking circuit includes a dummy memory cell coupled to a first dummy bit line, a second dummy bit line, and a dummy word line, a logic operation unit coupled to the dummy word line and to the first dummy bit line and configured to output a write feedback signal based on a logic operation of a signal on the dummy word line and a signal on the first dummy bit line, and a delay unit coupled to the dummy memory cell at a storage node. The write tracking circuit provides a correct feedback signal to the clock generation module to ensure normal operation of the peripheral circuit, when a data write operation to the dummy memory cell failed.