Memory Module Prefetch via 3D Stacked BLSA and TSV
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Solution Overview
Problem
Conventional DRAM chip architectures face limitations in increasing prefetch numbers without significantly expanding chip area, leading to a tradeoff between prefetch capabilities and chip size.
Innovation Solution
The proposed solution involves a memory module with a memory chip and a secondary semiconductor chip, utilizing bit-line sense amplifiers and main data lines to enhance prefetch access, allowing for increased prefetch numbers without expanding the chip area, by directly outputting amplified signals for further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the prefetch number of the DRAM is increased to achieve high bandwidth access, then the bandwidth access is improved, but the chip area is significantly increased
Solution Approach 1:
The patent introduces a third dimension (vertical stacking) by placing a secondary semiconductor chip above the memory chip, connected through through-silicon via (TSV) technology. This 3D architecture enables multiple prefetch paths to operate simultaneously without increasing the planar chip area, thereby achieving high bandwidth access while maintaining compact footprint.
Solution Approach 2:
The patent divides the prefetch functionality into multiple independent bit-line sense amplifier (BLSA) groups, where each group can operate autonomously. By segmenting the data output paths and enabling parallel operation of multiple BLSA groups across different chip layers, the system achieves increased prefetch number without proportionally increasing the area of individual components.
2Productivity
If the prefetch number is increased beyond conventional limits, then the bandwidth access is improved, but the internal access cycle time is extended
Solution Approach 1:
The patent implements preliminary action by pre-fetching data from multiple memory locations simultaneously through parallel BLSA groups before the main data transfer is complete. The secondary semiconductor chip receives and buffers data from multiple sources concurrently, preparing it for subsequent processing operations, thereby reducing the overall access cycle time despite increased prefetch number.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining multiple active data transfer paths through the 3D architecture. While one BLSA group is transferring data, other groups continue to fetch and prepare data, eliminating idle periods and maintaining continuous productive operation throughout the access cycle.
Data Source
AI summary
An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.