Multi-port Semiconductor Memory with Variable Access Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-port semiconductor memory devices have inflexible access paths between input/output ports and memory cells, limiting operational and test efficiency due to fixed access structures, which restricts high-speed and high-efficiency operations.
Innovation Solution
A semiconductor memory device with a select control unit that allows variable access paths between memory areas and input/output ports, enabling each memory area to be accessed through at least one port, and a method for reallocating memory areas for different ports to optimize access and testing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If access paths between input/output ports and memory cells are fixed in hardware structure, then device complexity is reduced and manufacturing is simplified, but operational efficiency and test efficiency are degraded due to inability to dynamically allocate memory areas to different ports
Solution Approach 1:
The patent implements dynamic access path configuration by introducing a select control unit that can dynamically change the connection between memory areas and input/output ports based on operational mode. The system transitions from fixed hardware connections to dynamically reconfigurable paths controlled by mode signals, allowing the same physical structure to serve multiple functional configurations.
Solution Approach 2:
The select control unit serves multiple functions: it configures access paths for normal multi-port operation, enables test operations by routing memory areas to test ports, and adapts the device to different operational requirements. This single control component provides universal configuration capability across different operating modes without requiring separate dedicated circuits for each function.
2Productivity
If all memory cells can be accessed through any of a plurality of input/output ports, then operational efficiency is improved through parallel access, but device complexity increases due to required control mechanisms
Solution Approach 1:
The memory array is divided into distinct memory areas (banks), and the select control unit segments the control function by independently configuring access paths for each memory area. This segmentation allows different memory areas to be accessed through different ports simultaneously, enabling parallel operations while keeping the control structure manageable through localized control of each segment.
Solution Approach 2:
The select control unit acts as an intermediary between the memory areas and input/output ports, mediating the access requests and dynamically routing signals through appropriate paths. This intermediary component simplifies the overall control structure by centralizing the decision-making logic for path selection, rather than requiring complex distributed control across all port-memory interfaces.
3Reliability
If separate testing is performed through each input/output port, then test coverage is improved, but test time increases due to sequential testing requirements
Solution Approach 1:
During test operations, the select control unit dynamically configures access paths to route all memory areas through a single designated test port. This dynamic reconfiguration enables comprehensive testing of all memory cells through one port simultaneously, rather than requiring sequential testing through multiple ports, thereby reducing test time while maintaining full test coverage.
Solution Approach 2:
The patent merges the testing function for all memory areas into a single test port by using the select control unit to consolidate access paths. Instead of distributing test operations across multiple ports sequentially, the system combines all test traffic through one port, achieving parallel testing of all memory areas and significantly reducing overall test duration.
Data Source
AI summary
A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.