Multi-Level Memory Cell Programming with Asynchronous Access
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Solution Overview
Problem
Multi-level memory cell programming faces challenges with threshold voltage drift, leading to reduced accuracy in read and write operations, as the threshold voltages associated with stored logic states can change over time, affecting the accuracy of state identification and requiring additional power-consuming pre-read operations to correct for drift.
Innovation Solution
Implementing an asynchronous access operation that stores a known logic state prior to write operations, allowing for the use of programming pulses with the same polarity, thereby reducing threshold voltage drift and conserving power and processing resources by avoiding polarity flips and pre-read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell programming is used, then write operations can be performed, but threshold voltage drift occurs leading to reduced accuracy in read and write operations
Solution Approach 1:
The patent applies preliminary action by performing an asynchronous access operation before the write operation to store a known logic state in the memory cell. This pre-action establishes a reference state that enables accurate programming without polarity flips, thereby preventing threshold voltage drift and maintaining both reliability and stability throughout the programming process.
2Measurement precision
If pre-read operations are performed to correct for drift, then accuracy of state identification improves, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the need for pre-read operations by using the asynchronous access operation to establish a known initial state. This removal of the corrective pre-read step reduces power consumption while maintaining measurement precision through the alternative mechanism of polarity-consistent programming pulses.
3Adaptability or versatility
If polarity flips are used in programming pulses, then different logic states can be programmed, but threshold voltage drift increases and processing resources are consumed
Solution Approach 1:
The patent uses periodic action by applying multiple programming pulses with the same polarity in sequence during the write operation. This periodic application of consistent-polarity pulses, enabled by the pre-established known state from the asynchronous access operation, maintains adaptability to program different logic states while eliminating the need for polarity flips and reducing processing overhead.
Data Source
AI summary
Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.