Variable Selector Memory Device for Failure Bit Isolation
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Solution Overview
Problem
Resistive memories, such as ReRAM, often experience failure bits that cannot be set to a predetermined resistance, leading to unpredictable and random errors, which negatively impact storage apparatus reliability.
Innovation Solution
A memory device with a selector having a variable electrical parameter that can be set to different levels, allowing the selector to be enabled or disabled, thereby controlling access to memory units and preventing failure bits from being accessed, while minimizing leakage current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory units are kept accessible in the memory array, then the storage capacity and accessibility are maximized, but failure bits can be accessed causing reliability degradation and increased power consumption due to sneak path currents
Solution Approach 1:
The memory array is segmented into multiple banks, and failure bits are isolated at the row or column level within these banks. This allows selective disabling of only the affected memory units while keeping the rest of the memory array operational, thereby maintaining reliability without excessive complexity.
Solution Approach 2:
Decoder circuits serve as intermediaries between the address input and the memory units. These decoders can be configured to disable specific rows or columns by preventing the activation of corresponding word lines or bit lines, thus isolating failure bits without requiring direct control of each memory unit.
2Ease of operation
If selectors are kept in enabled state to allow memory access, then data accessibility is improved, but leakage current increases and power consumption rises
Solution Approach 1:
The selectors are designed with dynamic controllable resistance states rather than fixed states. The resistance of selectors can be adjusted in real-time based on whether the associated memory unit is being accessed, allowing the system to transition between low-leakage (disabled) and high-accessibility (enabled) states as needed.
Solution Approach 2:
The electrical resistance parameter of the selectors is changed based on the access requirements. When a memory unit is not being accessed, the selector resistance is increased to disable access and reduce leakage current. When access is needed, the resistance is decreased to enable the selector, thus dynamically optimizing the balance between accessibility and power consumption.
3Productivity
If program operation is performed on all memory units, then storage capacity is maximized, but failure bits that cannot be programmed successfully degrade overall system reliability
Solution Approach 1:
Failure bits are extracted or isolated from the active memory array by disabling their corresponding selectors. This separation allows the majority of functional memory units to operate at full capacity while the failed units are removed from the accessible address space, maintaining both productivity and reliability.
Solution Approach 2:
The presence of failure bits is converted into a benefit by using them as indicators to adjust selector states. Instead of allowing failure bits to cause random errors, the system detects programming failures and uses this information to disable the corresponding selectors, thereby converting a harmful element into a means for improving overall system reliability through adaptive configuration.
Data Source
AI summary
A memory device includes a memory unit and a selector. The memory unit is configured to store data. The selector is coupled to the memory unit, and has a variable electrical parameter capable of being set to different levels. When the variable electrical parameter of the selector is set to a first level, the selector is turned on in response to an operation signal that is enabled, allowing the data stored in the memory unit to be accessed; when the variable electrical parameter of the selector is set to a second level, the selector remains turned off when receiving the operation signal that is enabled, prohibiting the data stored in the memory unit from being accessed.