Ferroelectric Memory Cell Imprint Mitigation via Periodic Rewriting
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Solution Overview
Problem
Ferroelectric memory cells experience performance degradation due to shifting ferroelectric domains over time, leading to imprint issues that affect read and write operations, particularly in non-volatile memory devices where data retention is crucial.
Innovation Solution
Implementing a method where a ferroelectric memory cell is periodically rewritten with an opposite logic state to mitigate domain shifting, using a timer or event-based triggers, and storing an indicator to maintain the intended logic state, thereby reducing bit errors and extending data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is stored in ferroelectric memory cells for extended periods, then non-volatile data retention is achieved, but ferroelectric domains shift causing performance degradation and imprint issues
Solution Approach 1:
The patent applies periodic action by implementing a timer that periodically triggers rewrite operations to memory cells that have stored data for a determined time period. This periodic intervention prevents ferroelectric domain shifting and imprint effects from degrading memory performance, thereby maintaining reliability while enabling extended data retention.
Solution Approach 2:
The patent uses preliminary action by proactively rewriting data in memory cells before ferroelectric domain shifts cause performance degradation. The timer predicts when imprint issues will occur and performs preventive rewrite operations, storing opposite logic states to counteract domain shifting effects before they manifest as read/write errors.
2Reliability
If memory cells are frequently rewritten to prevent imprint, then performance and reliability are maintained, but the complexity of memory management increases
Solution Approach 1:
The patent implements self-service by enabling memory cells to effectively manage their own maintenance needs. Each memory cell has an associated timer that autonomously tracks storage duration and triggers rewrite operations when appropriate, eliminating the need for complex external memory management logic while maintaining performance and reliability.
3Reliability
If opposite logic states are written to counteract domain shifting, then imprint effects are reduced, but additional write operations increase energy consumption
Solution Approach 1:
The patent applies feedback by using timers to monitor the storage duration in each memory cell and triggering rewrite operations only when the determined time period has elapsed. This feedback-based approach ensures that rewrite operations occur at optimal intervals to counteract domain shifting and maintain data integrity, while minimizing unnecessary write operations that would consume additional energy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains the reliability and performance of ferroelectric memory cells by reducing the impact of domain shifting, minimizing the need for frequent refresh operations and enhancing data retention over extended periods.
Implementation Method 1
A ferroelectric memory cell may include a ferroelectric capacitor that is written with a logic state
Implementation Method 2
A timer may be started when the logic state is stored in the ferroelectric memory cell and a current value of the timer may be compared with a pre-determined or dynamically configured value that corresponds to a configured time period
Data Source
AI summary
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.