Tri-State Logic Enable Circuit for Memory Bank Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices with multiple memory groups or banks experience significant time lags and data collisions due to long distances between memory groups and the need for numerous decoding control signal lines, leading to increased complexity and space requirements.
Innovation Solution
A memory device incorporating a control circuit with a tri-state logic enable circuit and address decoding circuit that temporarily stores address signals, synchronizes them with a synchronization signal, and generates enable signals to reduce time lag and data collisions by enabling only the necessary memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between different memory groups is increased to accommodate more memory banks, then the memory capacity is improved, but a large time lag occurs between the enable signals of different memory groups causing output data collision
Solution Approach 1:
The patent introduces a synchronization signal that is transmitted to all memory groups in advance to pre-synchronize the enable signals before data read operations. This preliminary synchronization action ensures that even though memory groups are physically distant, their enable signals are temporally aligned, preventing data collisions while maintaining expanded memory capacity.
Solution Approach 2:
The patent uses a synchronization signal as an intermediary mechanism between the control circuit and memory groups. This intermediary signal coordinates the timing of enable signals across all memory groups, resolving the time lag issue caused by increased distances between memory groups while preserving the benefit of expanded memory capacity.
2Quantity of substance
If there are more memory banks, then the memory capacity is improved, but many decoding control signal lines are required which require larger space
Solution Approach 1:
The patent merges the control functions for multiple memory banks into a unified control circuit that uses a common synchronization signal and shared decoding logic. Instead of having separate decoding control signal lines for each memory bank, the system combines these functions, reducing the total number of signal lines and the space required while maintaining support for multiple memory banks to achieve high memory capacity.
Solution Approach 2:
The synchronization signal and decoding circuit are designed to be universal, serving all memory groups simultaneously. A single synchronization signal line and shared decoding logic can control multiple memory banks, eliminating the need for dedicated control signal lines for each bank. This multi-functional approach reduces space requirements while supporting expanded memory capacity through multiple banks.
Data Source
AI summary
A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.