Memory Bypass Circuit for At-Speed Testing
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Solution Overview
Problem
Existing memory device testing methods face challenges in achieving at-speed access time comparable to actual read functions while incurring area penalties and performance overhead due to the use of multiplexers for bypassing the memory array during testing.
Innovation Solution
Implementing a clocked write-through memory bypass function that enables concurrent write and read operations without accessing the memory array, using a word line disable circuit, read/write activation circuit, internal clock generator, and write data input circuit to facilitate at-speed testing with minimal access time penalty and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer is used to create a logic bypass for testing, then testing of downstream logic can be performed without accessing the memory array, but access time is not comparable to actual read function and area penalty is incurred
Solution Approach 1:
The patent extracts the bypass functionality from a multiplexer-based implementation to a dedicated bypass circuit that operates in parallel with the memory array. This extraction allows the bypass path to operate independently with its own timing characteristics, achieving at-speed testing without the access time penalties of multiplexer-based solutions.
Solution Approach 2:
The patent introduces a dedicated bypass circuit as an intermediary element that mediates between the data input and data output paths during testing. This intermediary bypass circuit provides a direct connection that mimics the timing characteristics of actual memory read operations, enabling accurate at-speed testing of downstream logic.
2Adaptability or versatility
If a multiplexer is used to create a logic bypass for testing, then testing of downstream logic can be performed without accessing the memory array, but area penalty is incurred due to multiplexer implementation
Solution Approach 1:
The patent extracts the bypass functionality from a multiplexer-based implementation to a dedicated bypass circuit. This extraction eliminates the need for complex multiplexer logic and associated control circuitry, significantly reducing the area overhead while maintaining the ability to perform at-speed testing of downstream logic.
Solution Approach 2:
The patent employs a simplified bypass circuit design that uses basic logic elements rather than expensive multiplexer components. This approach prioritizes area efficiency while still achieving the essential testing functionality, effectively using simpler, more area-efficient components for the bypass path.
3Productivity
If asynchronous write-through circuitry is used for testing, then data can be forwarded from input to output without accessing memory array, but timing of data output is independent of access time and does not provide at-speed condition
Solution Approach 1:
The patent transforms the static, asynchronous bypass approach into a dynamic, clocked bypass circuit that operates in synchronization with the memory device's clock signal. This dynamic approach allows the bypass path to track and match the timing characteristics of actual memory read operations, providing accurate at-speed testing conditions.
Solution Approach 2:
The patent implements periodic clocking of the bypass circuit to match the periodic nature of memory read operations. By synchronizing the bypass path with the same clock signal that drives actual memory reads, the circuit achieves timing alignment that provides accurate at-speed testing of downstream logic.
Data Source
AI summary
A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.