Bit Line Sense Amplifier Isolation for Fast Data Writing
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Solution Overview
Problem
Conventional semiconductor memory devices experience longer bit line restoring times during data masking operations due to load effects from input/output lines, leading to unstable operations and decreased speed.
Innovation Solution
A semiconductor memory device with a bit line sense amplifier and shift control circuit that electrically separates the bit line pair from the input/output line pair using data masking signals, reducing restoring time through MOS transistor configurations and data masking control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bit line sense amplifier is electrically coupled to the input/output line pair during data masking operation, then the input/output circuit can buffer and provide data signals, but the restoring time of the bit line increases due to load effect
Solution Approach 1:
The patent divides the electrical connection between the bit line sense amplifier and input/output line pair into separable segments using switch circuits. During data masking operations, the switch circuits can disconnect the bit line pair from the input/output line pair, isolating the load effect. During normal operations, the connection is maintained for data buffering. This segmentation allows independent control of the two functional requirements.
Solution Approach 2:
The patent implements dynamic control of the electrical connection between the bit line sense amplifier and input/output line pair through control signals that adjust the state of switch circuits. The connection is dynamically established or disconnected based on the operation mode (data masking vs. normal operation), allowing the system to adapt its electrical topology to optimize performance for each specific operation type.
2Ease of operation
If the bit line sense amplifier maintains electrical coupling with input/output line pair for data buffering, then data can be buffered and provided to input/output pins, but the operation speed decreases due to longer restoring time
Solution Approach 1:
The patent segments the electrical path between the bit line sense amplifier and input/output line pair using controllable switch circuits. This segmentation enables the system to disconnect the bit line pair during data masking operations, eliminating the load effect that slows down bit line restoring. The segmentation preserves the data buffering capability during normal operations while removing the speed penalty during masking operations.
Solution Approach 2:
The patent employs dynamic switching control to adjust the electrical connection state between the bit line sense amplifier and input/output line pair based on operation mode. Control signals dynamically adjust the switch circuits to either connect (for data buffering) or disconnect (for fast restoring), allowing the system to optimize operation speed for data masking while maintaining data buffering functionality when needed.
Data Source
AI summary
A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.