Semiconductor Memory MRS Code Validation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices malfunction when an illegal Mode Register Set (MRS) code is inputted, as they decode such codes and operate in erroneous modes.
Innovation Solution
A semiconductor memory device with a first latch for MRS code latching, a code controller to generate a control signal based on specific bits, and a second latch to selectively latch and decode the output, ensuring that illegal MRS codes revert to a previous valid state, preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general MRS decoder is used to decode MRS codes, then the device can determine operation modes (CL, BL, BT), but it malfunctions when illegal MRS codes are inputted
Solution Approach 1:
The patent applies preliminary action by checking whether the MRS code is legal before decoding it. The operation mode determination unit first validates the MRS code received from the address pin, and only if it is legal does it proceed to decode the code to determine operation modes. This prevents illegal codes from causing malfunctions while still allowing valid codes to set the desired operation modes.
2Reliability
If MRS code validation is added to prevent illegal code malfunctions, then reliability improves, but device complexity increases
Solution Approach 1:
The patent merges the MRS code validation function with the existing operation mode determination unit. Rather than adding a separate validation module, the validation logic is integrated into the existing decoder structure, allowing the same unit to perform both validation and decoding operations. This reduces the increase in device complexity while still providing reliable malfunction prevention.
Data Source
AI summary
A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.