Semiconductor Memory Sensing Architecture With Delay Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced process technologies in semiconductor memory devices exhibit significant variability in element characteristics, leading to false sensing of logic states due to noise in the ground plane and power consumption issues during read operations.
Innovation Solution
A circuit arrangement with a delay circuit that activates the reference memory cell after the data memory cell is selected, enabling a sense amplifier to determine the logic state only after the reference memory cell has driven current at a higher rate than the data memory cell, and a latch to capture and disable the sense amplifier output to avoid false readings and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reference memory cell current is set close to 0 to reduce false sensing, then ground noise may cause false sensing of logic 1, but if set too high then weak bit line currents may cause false sensing of logic 0
Solution Approach 1:
The reference memory cell is activated before the data memory cell in a controlled sequence. The delay circuit ensures the reference cell is ready and stable before the data cell begins its transition, allowing the sense amplifier to compare against a known reference state rather than simultaneously transitioning cells which creates uncertainty during the critical sensing window
Solution Approach 2:
The patent implements dynamic control of the reference memory cell activation timing through the delay circuit. The reference cell current is dynamically adjusted by controlling when it is activated relative to the data cell, allowing optimization of the current difference during the sensing window to maintain reliable discrimination across process variations
2Device complexity
If simultaneous activation of data and reference memory cells is used, then the sensing operation is simple, but process variability causes false sensing due to timing mismatches
Solution Approach 1:
The reference memory cell is activated before the data memory cell through the delay circuit. This preliminary activation ensures the reference cell reaches its steady state current level first, creating a stable reference against which the data cell transition can be accurately measured, thereby improving discrimination accuracy despite added timing control
Solution Approach 2:
The sense amplifier naturally begins operating when the reference memory cell is activated, as the reference cell's current drives the differential pair. The system self-regulates by using the reference cell's activation as the trigger for sense amplifier operation, eliminating the need for separate complex control logic
3Measurement precision
If the sense amplifier operates continuously to ensure accurate sensing, then sensing accuracy is maintained, but power consumption increases
Solution Approach 1:
The sense amplifier operates periodically rather than continuously, being enabled only during the specific time window when the reference memory cell is activated and the data memory cell transitions. The latch circuit maintains the sensed output state after the sense amplifier is disabled, allowing accurate sensing to be achieved with brief periodic operation rather than continuous power consumption
Solution Approach 2:
The latch circuit provides feedback by capturing and holding the sense amplifier output state. Once the sense amplifier determines the logic state, the latch maintains this state even after the sense amplifier is disabled, eliminating the need for continuous sense amplifier operation and reducing power consumption while preserving sensing accuracy
Data Source
AI summary
A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated. The circuit arrangement further has a latch connected to an output of the sense amplifier, the latch capturing the output from the sense amplifier when the sense amplifier determines the logic state of the selected memory cell and sending a signal to the sense amplifier to disable itself.