Semiconductor Clock Signal Power Reduction via Extraction
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Solution Overview
Problem
Semiconductor memory devices face high power consumption due to the need for multiple frequency-divided clock signals to regenerate an internal clock signal, especially in devices with long clock lines, which increases power usage and reduces signal quality.
Innovation Solution
A semiconductor device design that generates only one frequency-divided clock signal during writing operations, reducing the need for multiple clock signals and thus lowering power consumption, while maintaining signal quality by using a frequency dividing circuit and a multiplier circuit to regenerate an internal clock signal with the same frequency as the external clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple frequency-divided clock signals are transmitted via long clock lines to regenerate an internal clock signal, then the internal clock signal quality is maintained, but power consumption increases due to the need for multiple high-capability drivers
Solution Approach 1:
The patent extracts only the necessary frequency-divided clock signal (one out of multiple) for transmission during write operations. By removing the unnecessary clock signals from the transmission path, the system reduces the number of drivers needed while still maintaining sufficient clock signal quality for internal operations, thereby reducing power consumption without sacrificing reliability
Solution Approach 2:
The patent dynamically adjusts the clock signal transmission strategy based on operational mode. During read operations, multiple frequency-divided clock signals are transmitted to maintain high signal quality. During write operations, only one frequency-divided clock signal is transmitted, reducing power consumption. This dynamic adaptation allows the system to optimize between reliability and power consumption based on actual operational needs
2Reliability
If multiple frequency-divided clock signals are transmitted to ensure accurate data transfer, then data transfer accuracy is improved, but the complexity of the clock distribution system increases
Solution Approach 1:
The patent extracts and transmits only the essential frequency-divided clock signal during write operations, removing unnecessary clock signals from the distribution system. This reduction in the number of transmitted clock signals directly decreases the complexity of the clock distribution system while maintaining sufficient timing accuracy for data transfer through the remaining signal
Solution Approach 2:
The patent applies partial action by transmitting only one frequency-divided clock signal during write operations instead of multiple signals. This partial transmission is sufficient to maintain data transfer accuracy for write operations, while significantly reducing the complexity of the clock distribution infrastructure required
Data Source
AI summary
Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.